mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-28 08:08:45 +00:00
629d04f530
Some cores support only AArch64 mode. In those cores, only a limited subset of the AArch32 system registers are implemented. Hence, if TF-A is supposed to run on AArch64-only cores, it must be compiled with CTX_INCLUDE_AARCH32_REGS=0. Currently, the default settings for compiling TF-A are with the AArch32 system registers included. So, if we compile TF-A the default way and attempt to run it on an AArch64-only core, we only get a runtime panic. Now a compile-time check has been added to ensure that this flag has the appropriate value when AArch64-only cores are included in the build. Change-Id: I298ec550037fafc9347baafb056926d149197d4c Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
66 lines
1.9 KiB
ArmAsm
66 lines
1.9 KiB
ArmAsm
/*
|
|
* Copyright (c) 2019, Arm Limited. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <asm_macros.S>
|
|
#include <cortex_a76ae.h>
|
|
#include <cpu_macros.S>
|
|
|
|
/* Hardware handled coherency */
|
|
#if HW_ASSISTED_COHERENCY == 0
|
|
#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled"
|
|
#endif
|
|
|
|
/* 64-bit only core */
|
|
#if CTX_INCLUDE_AARCH32_REGS == 1
|
|
#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
|
#endif
|
|
|
|
/* ---------------------------------------------
|
|
* HW will do the cache maintenance while powering down
|
|
* ---------------------------------------------
|
|
*/
|
|
func cortex_a76ae_core_pwr_dwn
|
|
/* ---------------------------------------------
|
|
* Enable CPU power down bit in power control register
|
|
* ---------------------------------------------
|
|
*/
|
|
mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1
|
|
orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK
|
|
msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0
|
|
isb
|
|
ret
|
|
endfunc cortex_a76ae_core_pwr_dwn
|
|
|
|
#if REPORT_ERRATA
|
|
/*
|
|
* Errata printing function for Cortex-A76AE. Must follow AAPCS.
|
|
*/
|
|
func cortex_a76ae_errata_report
|
|
ret
|
|
endfunc cortex_a76ae_errata_report
|
|
#endif /* REPORT_ERRATA */
|
|
|
|
/* ---------------------------------------------
|
|
* This function provides cortex_a76ae specific
|
|
* register information for crash reporting.
|
|
* It needs to return with x6 pointing to
|
|
* a list of register names in ascii and
|
|
* x8 - x15 having values of registers to be
|
|
* reported.
|
|
* ---------------------------------------------
|
|
*/
|
|
.section .rodata.cortex_a76ae_regs, "aS"
|
|
cortex_a76ae_regs: /* The ASCII list of register names to be reported */
|
|
.asciz "cpuectlr_el1", ""
|
|
|
|
func cortex_a76ae_cpu_reg_dump
|
|
adr x6, cortex_a76ae_regs
|
|
mrs x8, CORTEX_A76AE_CPUECTLR_EL1
|
|
ret
|
|
endfunc cortex_a76ae_cpu_reg_dump
|
|
|
|
declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, CPU_NO_RESET_FUNC, \
|
|
cortex_a76ae_core_pwr_dwn
|