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https://github.com/ARM-software/arm-trusted-firmware.git
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86f297a3e1
The base address for second DRAM varies across different platforms. So allow platforms to define second DRAM by moving Juno/SGM-775 specific definition of second DRAM base address to Juno/SGM-775 board definition respectively, SGI/RD specific definition of DRAM 2 base address to SGI board definition. Change-Id: I0ecd3a2bd600b6c7019c7f06f8c452952bd07cae Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>
69 lines
2 KiB
C
69 lines
2 KiB
C
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOARD_CSS_DEF_H
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#define BOARD_CSS_DEF_H
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#include <lib/utils_def.h>
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#include <plat/arm/board/common/v2m_def.h>
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#include <plat/arm/soc/common/soc_css_def.h>
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#include <plat/common/common_def.h>
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/*
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* Definitions common to all ARM CSS-based development platforms
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*/
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/* Platform ID address */
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#define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0
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/* Platform ID related accessors */
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#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f
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#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0
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#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00
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#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8
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#define BOARD_CSS_PLAT_TYPE_RTL 0x00
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#define BOARD_CSS_PLAT_TYPE_FPGA 0x01
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#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
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#define BOARD_CSS_PLAT_TYPE_FVP 0x03
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#ifndef __ASSEMBLER__
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#include <lib/mmio.h>
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#define BOARD_CSS_GET_PLAT_TYPE(addr) \
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((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
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>> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
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#endif /* __ASSEMBLER__ */
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/* Reserve the last block of flash for PSCI MEM PROTECT flag */
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#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/* UART related constants */
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#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
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#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
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#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
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#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
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#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE
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#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
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#endif /* BOARD_CSS_DEF_H */
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