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https://github.com/ARM-software/arm-trusted-firmware.git
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ed108b5605
This patch provides the following features and makes modifications listed below: - Individual APIAKey key generation for each CPU. - New key generation on every BL31 warm boot and TSP CPU On event. - Per-CPU storage of APIAKey added in percpu_data[] of cpu_data structure. - `plat_init_apiakey()` function replaced with `plat_init_apkey()` which returns 128-bit value and uses Generic timer physical counter value to increase the randomness of the generated key. The new function can be used for generation of all ARMv8.3-PAuth keys - ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`. - New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively; pauth_disable_el1()` and `pauth_disable_el3()` functions disable PAuth for EL1 and EL3 respectively; `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from cpu-data structure. - Combined `save_gp_pauth_registers()` function replaces calls to `save_gp_registers()` and `pauth_context_save()`; `restore_gp_pauth_registers()` replaces `pauth_context_restore()` and `restore_gp_registers()` calls. - `restore_gp_registers_eret()` function removed with corresponding code placed in `el3_exit()`. - Fixed the issue when `pauth_t pauth_ctx` structure allocated space for 12 uint64_t PAuth registers instead of 10 by removal of macro CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h` and assigning its value to CTX_PAUTH_REGS_END. - Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions in `msr spsel` instruction instead of hard-coded values. - Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI. Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARCH_FEATURES_H
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#define ARCH_FEATURES_H
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#include <stdbool.h>
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#include <arch_helpers.h>
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static inline bool is_armv7_gentimer_present(void)
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{
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/* The Generic Timer is always present in an ARMv8-A implementation */
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return true;
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}
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static inline bool is_armv8_2_ttcnp_present(void)
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{
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return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
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ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
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}
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static inline bool is_armv8_3_pauth_present(void)
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{
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uint64_t mask = (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) |
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(ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) |
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(ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) |
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(ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT);
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/* If any of the fields is not zero, PAuth is present */
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return (read_id_aa64isar1_el1() & mask) != 0U;
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}
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static inline bool is_armv8_4_ttst_present(void)
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{
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return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
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ID_AA64MMFR2_EL1_ST_MASK) == 1U;
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}
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static inline bool is_armv8_5_bti_present(void)
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{
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return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) &
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ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
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}
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static inline unsigned int get_armv8_5_mte_support(void)
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{
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return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
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ID_AA64PFR1_EL1_MTE_MASK);
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}
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#endif /* ARCH_FEATURES_H */
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