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79629b1a79
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY and its firmware, as well as the DDR controller. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
118 lines
3.9 KiB
C
118 lines
3.9 KiB
C
/*
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* Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DDRPHY_PHYINIT_USERCUSTOM_H
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#define DDRPHY_PHYINIT_USERCUSTOM_H
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#include <stdbool.h>
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#include <stdint.h>
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#include <ddrphy_csr_all_cdefines.h>
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#include <drivers/st/stm32mp2_ddr.h>
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/* Message Block Structure Definitions */
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#if STM32MP_DDR3_TYPE
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#include <mnpmusrammsgblock_ddr3.h>
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#elif STM32MP_DDR4_TYPE
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#include <mnpmusrammsgblock_ddr4.h>
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#else /* STM32MP_LPDDR4_TYPE */
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#include <mnpmusrammsgblock_lpddr4.h>
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#endif /* STM32MP_DDR3_TYPE */
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/*
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* -------------------------------------------------------------
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* Defines for Firmware Images
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* - indicate IMEM/DMEM address, size (bytes) and offsets.
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* -------------------------------------------------------------
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*
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* IMEM_SIZE max size of instruction memory.
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* DMEM_SIZE max size of data memory.
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*
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* IMEM_ST_ADDR start of IMEM address in memory.
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* DMEM_ST_ADDR start of DMEM address in memory.
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* DMEM_BIN_OFFSET start offset in DMEM memory (message block).
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*/
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#if STM32MP_DDR3_TYPE
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#define IMEM_SIZE 0x4C28U
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#define DMEM_SIZE 0x6C8U
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#elif STM32MP_DDR4_TYPE
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#define IMEM_SIZE 0x6D24U
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#define DMEM_SIZE 0x6CCU
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#else /* STM32MP_LPDDR4_TYPE */
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#define IMEM_SIZE 0x7E50U
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#define DMEM_SIZE 0x67CU
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#endif /* STM32MP_DDR3_TYPE */
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#define IMEM_ST_ADDR 0x50000U
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#define DMEM_ST_ADDR 0x54000U
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#define DMEM_BIN_OFFSET 0x200U
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/*
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* ------------------
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* Type definitions
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* ------------------
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*/
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/* A structure used to SRAM memory address space */
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enum return_offset_lastaddr {
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RETURN_OFFSET,
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RETURN_LASTADDR
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};
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/* Enumeration of instructions for PhyInit Register Interface */
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enum reginstr {
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STARTTRACK, /* Start register tracking */
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STOPTRACK, /* Stop register tracking */
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SAVEREGS, /* Save(read) tracked register values */
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RESTOREREGS, /* Restore (write) saved register values */
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};
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/* Data structure to store register address/value pairs */
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struct reg_addr_val {
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uint32_t address; /* Register address */
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uint16_t value; /* Register value */
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};
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/* Target CSR for the impedance value for ddrphy_phyinit_mapdrvstren() */
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enum drvtype {
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DRVSTRENFSDQP,
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DRVSTRENFSDQN,
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ODTSTRENP,
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ODTSTRENN,
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ADRVSTRENP,
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ADRVSTRENN
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};
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/*
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* -------------------------------------------------------------
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* Fixed Function prototypes
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* -------------------------------------------------------------
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*/
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int ddrphy_phyinit_sequence(struct stm32mp_ddr_config *config, bool skip_training, bool reten);
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int ddrphy_phyinit_restore_sequence(void);
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int ddrphy_phyinit_c_initphyconfig(struct stm32mp_ddr_config *config,
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struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t *ardptrinitval);
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void ddrphy_phyinit_d_loadimem(void);
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void ddrphy_phyinit_progcsrskiptrain(struct stm32mp_ddr_config *config,
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struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t ardptrinitval);
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int ddrphy_phyinit_f_loaddmem(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d);
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int ddrphy_phyinit_g_execfw(void);
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void ddrphy_phyinit_i_loadpieimage(struct stm32mp_ddr_config *config, bool skip_training);
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void ddrphy_phyinit_loadpieprodcode(void);
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int ddrphy_phyinit_mapdrvstren(uint32_t drvstren_ohm, enum drvtype targetcsr);
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int ddrphy_phyinit_calcmb(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d);
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void ddrphy_phyinit_writeoutmem(uint32_t *mem, uint32_t mem_offset, uint32_t mem_size);
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void ddrphy_phyinit_writeoutmsgblk(uint16_t *mem, uint32_t mem_offset, uint32_t mem_size);
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int ddrphy_phyinit_isdbytedisabled(struct stm32mp_ddr_config *config,
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struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t dbytenumber);
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int ddrphy_phyinit_trackreg(uint32_t adr);
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int ddrphy_phyinit_reginterface(enum reginstr myreginstr, uint32_t adr, uint16_t dat);
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void ddrphy_phyinit_usercustom_custompretrain(struct stm32mp_ddr_config *config);
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int ddrphy_phyinit_usercustom_g_waitfwdone(void);
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int ddrphy_phyinit_usercustom_saveretregs(struct stm32mp_ddr_config *config);
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#endif /* DDRPHY_PHYINIT_USERCUSTOM_H */
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