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https://github.com/ARM-software/arm-trusted-firmware.git
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ec3c10039b
This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They do not have to be saved and restored either. The M, WXN and optionally the C bit are set in the enable_mmu_elX() function. This is done during both the warm and cold boot paths. Fixes ARM-software/tf-issues#226 Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
157 lines
5.2 KiB
ArmAsm
157 lines
5.2 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <psci.h>
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#include <xlat_tables.h>
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.globl psci_aff_on_finish_entry
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.globl psci_aff_suspend_finish_entry
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.globl __psci_cpu_off
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.globl __psci_cpu_suspend
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.globl psci_power_down_wfi
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/* -----------------------------------------------------
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* This cpu has been physically powered up. Depending
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* upon whether it was resumed from suspend or simply
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* turned on, call the common power on finisher with
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* the handlers (chosen depending upon original state).
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* -----------------------------------------------------
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*/
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func psci_aff_on_finish_entry
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adr x23, psci_afflvl_on_finishers
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b psci_aff_common_finish_entry
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psci_aff_suspend_finish_entry:
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adr x23, psci_afflvl_suspend_finishers
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psci_aff_common_finish_entry:
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#if !RESET_TO_BL31
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks. Also, set
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* the EL3 exception endianess to little-endian.
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* It can be assumed that BL3-1 entrypoint code
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* will do this when RESET_TO_BL31 is set. The
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* same assumption cannot be made when another
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* boot loader executes before BL3-1 in the warm
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* boot path e.g. BL1.
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* ---------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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#endif
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/* ---------------------------------------------
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* Initialise the pcpu cache pointer for the CPU
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* ---------------------------------------------
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*/
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bl init_cpu_data_ptr
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/* ---------------------------------------------
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* Set the exception vectors
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* ---------------------------------------------
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*/
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adr x0, runtime_exceptions
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msr vbar_el3, x0
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isb
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/* ---------------------------------------------
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* Use SP_EL0 for the C runtime stack.
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* ---------------------------------------------
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*/
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msr spsel, #0
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/* --------------------------------------------
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* Give ourselves a stack whose memory will be
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* marked as Normal-IS-WBWA when the MMU is
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* enabled.
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* --------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_stack
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/* --------------------------------------------
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* Enable the MMU with the DCache disabled. It
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* is safe to use stacks allocated in normal
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* memory as a result. All memory accesses are
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* marked nGnRnE when the MMU is disabled. So
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* all the stack writes will make it to memory.
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* All memory accesses are marked Non-cacheable
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* when the MMU is enabled but D$ is disabled.
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* So used stack memory is guaranteed to be
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* visible immediately after the MMU is enabled
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* Enabling the DCache at the same time as the
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* MMU can lead to speculatively fetched and
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* possibly stale stack memory being read from
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* other caches. This can lead to coherency
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* issues.
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* --------------------------------------------
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*/
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mov x0, #DISABLE_DCACHE
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bl bl31_plat_enable_mmu
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/* ---------------------------------------------
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* Call the finishers starting from affinity
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* level 0.
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* ---------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl get_power_on_target_afflvl
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cmp x0, xzr
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b.lt _panic
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mov x2, x23
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mov x1, x0
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mov x0, #MPIDR_AFFLVL0
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bl psci_afflvl_power_on_finish
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b el3_exit
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_panic:
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b _panic
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/* --------------------------------------------
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* This function is called to indicate to the
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* power controller that it is safe to power
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* down this cpu. It should not exit the wfi
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* and will be released from reset upon power
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* up. 'wfi_spill' is used to catch erroneous
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* exits from wfi.
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* --------------------------------------------
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*/
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func psci_power_down_wfi
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dsb sy // ensure write buffer empty
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wfi
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wfi_spill:
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b wfi_spill
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