Achin Gupta ec3c10039b Simplify management of SCTLR_EL3 and SCTLR_EL1 ... This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They do not have to be saved and restored either. The M, WXN and optionally the C bit are set in the enable_mmu_elX() function. This is done during both the warm and cold boot paths. Fixes ARM-software/tf-issues#226 Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069		2014-07-28 10:10:22 +01:00
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aarch64	Simplify management of SCTLR_EL3 and SCTLR_EL1	2014-07-28 10:10:22 +01:00
bl31.ld.S	fvp: Reuse BL1 and BL2 memory through image overlaying	2014-07-10 16:34:54 +01:00
bl31.mk	Remove coherent stack usage from the warm boot path	2014-07-19 23:31:53 +01:00
bl31_main.c	Remove all checkpatch errors from codebase	2014-06-24 12:50:00 +01:00
context_mgmt.c	Remove all checkpatch errors from codebase	2014-06-24 12:50:00 +01:00
cpu_data_array.c	Per-cpu data cache restructuring	2014-06-16 21:30:32 +01:00
interrupt_mgmt.c	Introduce interrupt registration framework in BL3-1	2014-05-22 17:46:56 +01:00
runtime_svc.c	Remove all checkpatch errors from codebase	2014-06-24 12:50:00 +01:00