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https://github.com/ARM-software/arm-trusted-firmware.git
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b0f2361a1a
In order to allow the use of PCIe cards such as graphics cards, whose demands for BAR space are typically much higher than those of network or SATA/USB cards, reconfigure the I/O windows so we can declare two MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64 one at 0x8_0000_0000. In addition, this will leave ample room for an ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB) For compatibility with older kernels or firmware, leave the original 16 MB window in place as well. Change-Id: Ia8177194e542078772f90941eced81b231c16887 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
196 lines
5 KiB
C
196 lines
5 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <armada_common.h>
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/*
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* If bootrom is currently at BLE there's no need to include the memory
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* maps structure at this point
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*/
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#include <mvebu_def.h>
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* AMB Configuration
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*****************************************************************************
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*/
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struct addr_map_win amb_memory_map[] = {
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/* CP1 SPI1 CS0 Direct Mode access */
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{0xf900, 0x1000000, AMB_SPI1_CS0_ID},
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};
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int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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*win = amb_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(amb_memory_map);
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return 0;
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}
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#endif
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/*****************************************************************************
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* IO WIN Configuration
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*****************************************************************************
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*/
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struct addr_map_win io_win_memory_map[] = {
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/* CP1 (MCI0) internal regs */
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{0x00000000f4000000, 0x2000000, MCI_0_TID},
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#ifndef IMAGE_BLE
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/* PCIe0 and SPI1_CS0 (RUNIT) on CP1*/
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{0x00000000f9000000, 0x2000000, MCI_0_TID},
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/* PCIe1 on CP1*/
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{0x00000000fb000000, 0x1000000, MCI_0_TID},
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/* PCIe2 on CP1*/
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{0x00000000fc000000, 0x1000000, MCI_0_TID},
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/* MCI 0 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
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/* MCI 1 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
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#endif
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};
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uint32_t marvell_get_io_win_gcr_target(int ap_index)
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{
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return PIDI_TID;
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}
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int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = io_win_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(io_win_memory_map);
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return 0;
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}
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* IOB Configuration
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*****************************************************************************
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*/
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struct addr_map_win iob_memory_map_cp0[] = {
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/* CP0 */
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/* PEX1_X1 window */
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{0x00000000f7000000, 0x1000000, PEX1_TID},
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/* PEX2_X1 window */
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{0x00000000f8000000, 0x1000000, PEX2_TID},
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/* PEX0_X4 window */
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{0x00000000f6000000, 0x1000000, PEX0_TID},
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{0x00000000c0000000, 0x30000000, PEX0_TID},
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{0x0000000800000000, 0x100000000, PEX0_TID},
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};
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struct addr_map_win iob_memory_map_cp1[] = {
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/* CP1 */
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/* SPI1_CS0 (RUNIT) window */
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{0x00000000f9000000, 0x1000000, RUNIT_TID},
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/* PEX1_X1 window */
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{0x00000000fb000000, 0x1000000, PEX1_TID},
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/* PEX2_X1 window */
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{0x00000000fc000000, 0x1000000, PEX2_TID},
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/* PEX0_X4 window */
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{0x00000000fa000000, 0x1000000, PEX0_TID}
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};
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int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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switch (base) {
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case MVEBU_CP_REGS_BASE(0):
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*win = iob_memory_map_cp0;
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*size = ARRAY_SIZE(iob_memory_map_cp0);
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return 0;
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case MVEBU_CP_REGS_BASE(1):
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*win = iob_memory_map_cp1;
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*size = ARRAY_SIZE(iob_memory_map_cp1);
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return 0;
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default:
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*size = 0;
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*win = 0;
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return 1;
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}
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}
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#endif
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/*****************************************************************************
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* CCU Configuration
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*****************************************************************************
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*/
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struct addr_map_win ccu_memory_map[] = {
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#ifdef IMAGE_BLE
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{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
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#else
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{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
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{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
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{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
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#endif
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};
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uint32_t marvell_get_ccu_gcr_target(int ap)
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{
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return DRAM_0_TID;
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}
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int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = ccu_memory_map;
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*size = ARRAY_SIZE(ccu_memory_map);
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return 0;
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}
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* SoC PM configuration
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*****************************************************************************
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*/
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/* CP GPIO should be used and the GPIOs should be within same GPIO register */
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struct power_off_method pm_cfg = {
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.type = PMIC_GPIO,
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.cfg.gpio.pin_count = 1,
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.cfg.gpio.info = {{0, 35} },
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.cfg.gpio.step_count = 7,
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.cfg.gpio.seq = {1, 0, 1, 0, 1, 0, 1},
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.cfg.gpio.delay_ms = 10,
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};
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void *plat_marvell_get_pm_cfg(void)
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{
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/* Return the PM configurations */
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return &pm_cfg;
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}
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/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
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#else
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/*****************************************************************************
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* SKIP IMAGE Configuration
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*****************************************************************************
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*/
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#if PLAT_RECOVERY_IMAGE_ENABLE
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struct skip_image skip_im = {
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.detection_method = GPIO,
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.info.gpio.num = 33,
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.info.gpio.button_state = HIGH,
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.info.test.cp_ap = CP,
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.info.test.cp_index = 0,
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};
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void *plat_marvell_get_skip_image_data(void)
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{
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/* Return the skip_image configurations */
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return &skip_im;
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}
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#endif
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#endif
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