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42a293379e
Some of COMPHY parameters depends on the hw connection between the SoC and the PHY, which can vary on different boards e.g. due to different wires length. Define the "porting layer" with some defaults parameters. It ease updating static values which needs to be updated due to board differences, which are now grouped in one place. Example porting layer for a8k-db is under: plat/marvell/a8k/a80x0/board/phy-porting-layer.h If for some boards parameters are not defined (missing phy-porting-layer.h), the default values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the following compilation warning is show: "Using default comphy params - you may need to suit them to your board". The common COMPHY driver code is extracted in order to be shared with future COMPHY driver for A3700 SoC platforms Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
167 lines
4.9 KiB
C
167 lines
4.9 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef __PHY_PORTING_LAYER_H
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#define __PHY_PORTING_LAYER_H
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#define MAX_LANE_NR 6
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static const struct xfi_params
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xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
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/* AP0 */
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{
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/* CP 0 */
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{
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{ 0 }, /* Comphy0 */
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{ 0 }, /* Comphy1 */
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{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
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.align90 = 0x5f,
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.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
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.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
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.g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
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.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
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.valid = 0x1 }, /* Comphy2 */
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{ 0 }, /* Comphy3 */
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{ 0 }, /* Comphy4 */
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{ 0 }, /* Comphy5 */
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},
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/* CP 1 */
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{
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{ 0 }, /* Comphy0 */
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{ 0 }, /* Comphy1 */
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{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
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.align90 = 0x5f,
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.g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
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.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
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.g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
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.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
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.valid = 0x1 }, /* Comphy2 */
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{ 0 }, /* Comphy3 */
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{ 0 }, /* Comphy4 */
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{ 0 }, /* Comphy5 */
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},
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},
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};
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static const struct sata_params
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sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
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/* AP0 */
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{
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/* CP 0 */
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{
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{ 0 }, /* Comphy0 */
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{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
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.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
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.g1_emph_en = 0x1, .g2_emph_en = 0x1,
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.g3_emph_en = 0x1,
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.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
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.g3_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
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.g3_tx_emph_en = 0x0,
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.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
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.g3_tx_emph = 0x1,
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.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
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.g3_ffe_cap_sel = 0xf,
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.align90 = 0x61,
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.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
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.g3_rx_selmuff = 0x3,
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.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
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.g3_rx_selmufi = 0x3,
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.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
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.g3_rx_selmupf = 0x2,
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.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
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.g3_rx_selmupi = 0x2,
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.valid = 0x1
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}, /* Comphy1 */
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{ 0 }, /* Comphy2 */
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{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
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.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
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.g1_emph_en = 0x1, .g2_emph_en = 0x1,
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.g3_emph_en = 0x1,
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.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
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.g3_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
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.g3_tx_emph_en = 0x0,
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.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
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.g3_tx_emph = 0x1,
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.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
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.g3_ffe_cap_sel = 0xf,
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.align90 = 0x61,
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.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
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.g3_rx_selmuff = 0x3,
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.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
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.g3_rx_selmufi = 0x3,
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.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
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.g3_rx_selmupf = 0x2,
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.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
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.g3_rx_selmupi = 0x2,
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.valid = 0x1
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}, /* Comphy3 */
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{ 0 }, /* Comphy4 */
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{ 0 }, /* Comphy5 */
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},
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/* CP 1 */
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{
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{ 0 }, /* Comphy0 */
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{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
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.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
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.g1_emph_en = 0x1, .g2_emph_en = 0x1,
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.g3_emph_en = 0x1,
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.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
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.g3_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
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.g3_tx_emph_en = 0x0,
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.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
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.g3_tx_emph = 0x1,
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.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
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.g3_ffe_cap_sel = 0xf,
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.align90 = 0x61,
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.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
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.g3_rx_selmuff = 0x3,
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.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
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.g3_rx_selmufi = 0x3,
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.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
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.g3_rx_selmupf = 0x2,
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.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
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.g3_rx_selmupi = 0x2,
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.valid = 0x1
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}, /* Comphy1 */
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{ 0 }, /* Comphy2 */
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{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
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.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
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.g1_emph_en = 0x1, .g2_emph_en = 0x1,
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.g3_emph_en = 0x1,
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.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
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.g3_tx_amp_adj = 0x1,
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.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
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.g3_tx_emph_en = 0x0,
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.g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
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.g3_tx_emph = 0x1,
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.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
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.g3_ffe_cap_sel = 0xf,
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.align90 = 0x61,
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.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
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.g3_rx_selmuff = 0x3,
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.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
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.g3_rx_selmufi = 0x3,
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.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
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.g3_rx_selmupf = 0x2,
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.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
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.g3_rx_selmupi = 0x2,
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.valid = 0x1
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}, /* Comphy3 */
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{ 0 }, /* Comphy4 */
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{ 0 }, /* Comphy5 */
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},
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},
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};
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#endif /* __PHY_PORTING_LAYER_H */
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