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https://github.com/ARM-software/arm-trusted-firmware.git
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1e66bacb71
Add supprot for Marvell platforms based on Armada-37xx SoC. This includes support for the official Armada-3720 modular development board and EspressoBin community board. The Armada-37xx SoC contains dual Cortex-A53 Application CPU, single secure CPU (Cortex-M3) and the following interfaces: - SATA 3.0 - USB 3.0 and USB 2.0 - PCIe - SDIO (supports boot from eMMC) - SPI - UART - I2c - Gigabit Ethernet Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
276 lines
7.1 KiB
C
276 lines
7.1 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <dram_win.h>
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#include <marvell_plat_priv.h>
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#include <mmio.h>
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#include <mvebu.h>
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#include <plat_marvell.h>
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#include <string.h>
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/* Armada 3700 has 5 configurable windows */
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#define MV_CPU_WIN_NUM 5
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#define CPU_WIN_DISABLED 0
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#define CPU_WIN_ENABLED 1
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/*
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* There are 2 different cpu decode window configuration cases:
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* - DRAM size is not over 2GB;
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* - DRAM size is 4GB.
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*/
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enum cpu_win_config_num {
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CPU_WIN_CONFIG_DRAM_NOT_OVER_2GB = 0,
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CPU_WIN_CONFIG_DRAM_4GB,
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CPU_WIN_CONFIG_MAX
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};
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enum cpu_win_target {
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CPU_WIN_TARGET_DRAM = 0,
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CPU_WIN_TARGET_INTERNAL_REG,
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CPU_WIN_TARGET_PCIE,
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CPU_WIN_TARGET_PCIE_OVER_MCI,
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CPU_WIN_TARGET_BOOT_ROM,
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CPU_WIN_TARGET_MCI_EXTERNAL,
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CPU_WIN_TARGET_RWTM_RAM = 7,
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CPU_WIN_TARGET_CCI400_REG
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};
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struct cpu_win_configuration {
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uint32_t enabled;
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enum cpu_win_target target;
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uint64_t base_addr;
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uint64_t size;
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uint64_t remap_addr;
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};
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struct cpu_win_configuration mv_cpu_wins[CPU_WIN_CONFIG_MAX][MV_CPU_WIN_NUM] = {
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/*
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* When total dram size is not over 2GB:
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* DDR window 0 is configured in tim header, its size may be not 512MB,
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* but the actual dram size, no need to configure it again;
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* other cpu windows are kept as default.
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*/
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{
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/* enabled
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* target
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* base
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* size
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* remap
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*/
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_DRAM,
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0x0,
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0x08000000,
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0x0},
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_MCI_EXTERNAL,
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0xe0000000,
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0x08000000,
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0xe0000000},
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_PCIE,
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0xe8000000,
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0x08000000,
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0xe8000000},
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_RWTM_RAM,
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0xf0000000,
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0x00020000,
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0x1fff0000},
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_PCIE_OVER_MCI,
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0x80000000,
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0x10000000,
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0x80000000},
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},
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/*
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* If total dram size is more than 2GB, now there is only one case - 4GB
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* dram; we will use below cpu windows configurations:
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* - Internal Regs, CCI-400, Boot Rom and PCIe windows are kept as
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* default;
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* - Use 4 CPU decode windows for DRAM, which cover 3.375GB DRAM;
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* DDR window 0 is configured in tim header with 2GB size, no need to
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* configure it again here;
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*
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* 0xFFFFFFFF ---> |-----------------------|
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* | Boot ROM | 64KB
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* 0xFFF00000 ---> +-----------------------+
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* : :
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* 0xF0000000 ---> |-----------------------|
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* | PCIE | 128 MB
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* 0xE8000000 ---> |-----------------------|
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* | DDR window 3 | 128 MB
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* 0xE0000000 ---> +-----------------------+
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* : :
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* 0xD8010000 ---> |-----------------------|
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* | CCI Regs | 64 KB
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* 0xD8000000 ---> +-----------------------+
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* : :
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* : :
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* 0xD2000000 ---> +-----------------------+
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* | Internal Regs | 32MB
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* 0xD0000000 ---> |-----------------------|
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* | DDR window 2 | 256 MB
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* 0xC0000000 ---> |-----------------------|
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* | |
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* | DDR window 1 | 1 GB
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* | |
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* 0x80000000 ---> |-----------------------|
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* | |
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* | |
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* | DDR window 0 | 2 GB
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* | |
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* | |
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* 0x00000000 ---> +-----------------------+
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*/
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{
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/* win_id
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* target
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* base
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* size
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* remap
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*/
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_DRAM,
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0x0,
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0x80000000,
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0x0},
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_DRAM,
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0x80000000,
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0x40000000,
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0x80000000},
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_DRAM,
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0xc0000000,
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0x10000000,
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0xc0000000},
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_DRAM,
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0xe0000000,
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0x08000000,
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0xe0000000},
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{CPU_WIN_ENABLED,
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CPU_WIN_TARGET_PCIE,
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0xe8000000,
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0x08000000,
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0xe8000000},
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},
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};
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/*
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* dram_win_map_build
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*
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* This function builds cpu dram windows mapping
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* which includes base address and window size by
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* reading cpu dram decode windows registers.
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*
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* @input: N/A
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*
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* @output:
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* - win_map: cpu dram windows mapping
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*
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* @return: N/A
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*/
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void dram_win_map_build(struct dram_win_map *win_map)
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{
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int32_t win_id;
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struct dram_win *win;
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uint32_t base_reg, ctrl_reg, size_reg, enabled, target;
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memset(win_map, 0, sizeof(struct dram_win_map));
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for (win_id = 0; win_id < DRAM_WIN_MAP_NUM_MAX; win_id++) {
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ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id));
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target = (ctrl_reg & CPU_DEC_CR_WIN_TARGET_MASK) >>
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CPU_DEC_CR_WIN_TARGET_OFFS;
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enabled = ctrl_reg & CPU_DEC_CR_WIN_ENABLE;
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/* Ignore invalid and non-dram windows*/
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if ((enabled == 0) || (target != DRAM_CPU_DEC_TARGET_NUM))
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continue;
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win = win_map->dram_windows + win_map->dram_win_num;
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base_reg = mmio_read_32(CPU_DEC_WIN_BASE_REG(win_id));
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size_reg = mmio_read_32(CPU_DEC_WIN_SIZE_REG(win_id));
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/* Base reg [15:0] corresponds to transaction address [39:16] */
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win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >>
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CPU_DEC_BR_BASE_OFFS;
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win->base_addr *= CPU_DEC_CR_WIN_SIZE_ALIGNMENT;
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/*
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* Size reg [15:0] is programmed from LSB to MSB as a sequence
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* of 1s followed by a sequence of 0s and the number of 1s
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* specifies the size of the window in 64 KB granularity,
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* for example, a value of 00FFh specifies 256 x 64 KB = 16 MB
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*/
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win->win_size = (size_reg & CPU_DEC_CR_WIN_SIZE_MASK) >>
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CPU_DEC_CR_WIN_SIZE_OFFS;
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win->win_size = (win->win_size + 1) *
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CPU_DEC_CR_WIN_SIZE_ALIGNMENT;
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win_map->dram_win_num++;
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}
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}
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static void cpu_win_set(uint32_t win_id, struct cpu_win_configuration *win_cfg)
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{
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uint32_t base_reg, ctrl_reg, size_reg, remap_reg;
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/* Disable window */
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ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id));
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ctrl_reg &= ~CPU_DEC_CR_WIN_ENABLE;
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mmio_write_32(CPU_DEC_WIN_CTRL_REG(win_id), ctrl_reg);
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/* For an disabled window, only disable it. */
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if (!win_cfg->enabled)
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return;
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/* Set Base Register */
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base_reg = (uint32_t)(win_cfg->base_addr /
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CPU_DEC_CR_WIN_SIZE_ALIGNMENT);
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base_reg <<= CPU_DEC_BR_BASE_OFFS;
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base_reg &= CPU_DEC_BR_BASE_MASK;
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mmio_write_32(CPU_DEC_WIN_BASE_REG(win_id), base_reg);
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/* Set Remap Register with the same value
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* as the <Base> field in Base Register
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*/
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remap_reg = (uint32_t)(win_cfg->remap_addr /
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CPU_DEC_CR_WIN_SIZE_ALIGNMENT);
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remap_reg <<= CPU_DEC_RLR_REMAP_LOW_OFFS;
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remap_reg &= CPU_DEC_RLR_REMAP_LOW_MASK;
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mmio_write_32(CPU_DEC_REMAP_LOW_REG(win_id), remap_reg);
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/* Set Size Register */
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size_reg = (win_cfg->size / CPU_DEC_CR_WIN_SIZE_ALIGNMENT) - 1;
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size_reg <<= CPU_DEC_CR_WIN_SIZE_OFFS;
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size_reg &= CPU_DEC_CR_WIN_SIZE_MASK;
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mmio_write_32(CPU_DEC_WIN_SIZE_REG(win_id), size_reg);
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/* Set Control Register - set target id and enable window */
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ctrl_reg &= ~CPU_DEC_CR_WIN_TARGET_MASK;
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ctrl_reg |= (win_cfg->target << CPU_DEC_CR_WIN_TARGET_OFFS);
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ctrl_reg |= CPU_DEC_CR_WIN_ENABLE;
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mmio_write_32(CPU_DEC_WIN_CTRL_REG(win_id), ctrl_reg);
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}
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void cpu_wins_init(void)
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{
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uint32_t cfg_idx, win_id;
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if (mvebu_get_dram_size(MVEBU_REGS_BASE) <= _2GB_)
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cfg_idx = CPU_WIN_CONFIG_DRAM_NOT_OVER_2GB;
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else
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cfg_idx = CPU_WIN_CONFIG_DRAM_4GB;
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/* Window 0 is configured always for DRAM in tim header
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* already, no need to configure it again here
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*/
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for (win_id = 1; win_id < MV_CPU_WIN_NUM; win_id++)
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cpu_win_set(win_id, &mv_cpu_wins[cfg_idx][win_id]);
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}
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