mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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1e66bacb71
Add supprot for Marvell platforms based on Armada-37xx SoC. This includes support for the official Armada-3720 modular development board and EspressoBin community board. The Armada-37xx SoC contains dual Cortex-A53 Application CPU, single secure CPU (Cortex-M3) and the following interfaces: - SATA 3.0 - USB 3.0 and USB 2.0 - PCIe - SDIO (supports boot from eMMC) - SPI - UART - I2c - Gigabit Ethernet Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
134 lines
3.4 KiB
ArmAsm
134 lines
3.4 KiB
ArmAsm
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef __MARVELL_MACROS_S__
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#define __MARVELL_MACROS_S__
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#include <cci.h>
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#include <gic_common.h>
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#include <gicv2.h>
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#include <gicv3.h>
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#include <platform_def.h>
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/*
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* These Macros are required by ATF
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*/
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.section .rodata.gic_reg_name, "aS"
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/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
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gicc_regs:
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.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
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#ifdef USE_CCI
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/* Applicable only to GICv3 with SRE enabled */
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icc_regs:
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.asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
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#endif
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/* Registers common to both GICv2 and GICv3 */
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
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" Offset:\t\t\tvalue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t0x"
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/* ---------------------------------------------
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* The below utility macro prints out relevant GIC
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* registers whenever an unhandled exception is
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* taken in BL31 on ARM standard platforms.
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* Expects: GICD base in x16, GICC base in x17
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* Clobbers: x0 - x10, sp
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* ---------------------------------------------
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*/
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.macro marvell_print_gic_regs
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/* Check for GICv3 system register access */
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mrs x7, id_aa64pfr0_el1
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ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
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cmp x7, #1
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b.ne print_gicv2
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/* Check for SRE enable */
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mrs x8, ICC_SRE_EL3
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tst x8, #ICC_SRE_SRE_BIT
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b.eq print_gicv2
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#ifdef USE_CCI
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/* Load the icc reg list to x6 */
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adr x6, icc_regs
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/* Load the icc regs to gp regs used by str_in_crash_buf_print */
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mrs x8, ICC_HPPIR0_EL1
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mrs x9, ICC_HPPIR1_EL1
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mrs x10, ICC_CTLR_EL3
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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#endif
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b print_gic_common
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print_gicv2:
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/* Load the gicc reg list to x6 */
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adr x6, gicc_regs
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/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
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ldr w8, [x17, #GICC_HPPIR]
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ldr w9, [x17, #GICC_AHPPIR]
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ldr w10, [x17, #GICC_CTLR]
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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print_gic_common:
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/* Print the GICD_ISPENDR regs */
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add x7, x16, #GICD_ISPENDR
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adr x4, gicd_pend_reg
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bl asm_print_str
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gicd_ispendr_loop:
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sub x4, x7, x16
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cmp x4, #0x280
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b.eq exit_print_gic_regs
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bl asm_print_hex
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adr x4, spacer
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bl asm_print_str
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ldr x4, [x7], #8
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bl asm_print_hex
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adr x4, newline
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bl asm_print_str
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b gicd_ispendr_loop
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exit_print_gic_regs:
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.endm
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.section .rodata.cci_reg_name, "aS"
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cci_iface_regs:
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.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
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/* ------------------------------------------------
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* The below required platform porting macro prints
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* out relevant interconnect registers whenever an
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* unhandled exception is taken in BL31.
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* Clobbers: x0 - x9, sp
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* ------------------------------------------------
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*/
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.macro print_cci_regs
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#ifdef USE_CCI
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adr x6, cci_iface_regs
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/* Store in x7 the base address of the first interface */
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mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
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PLAT_MARVELL_CCI_CLUSTER0_SL_IFACE_IX))
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ldr w8, [x7, #SNOOP_CTRL_REG]
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/* Store in x7 the base address of the second interface */
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mov_imm x7, (PLAT_MARVELL_CCI_BASE + SLAVE_IFACE_OFFSET( \
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PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX))
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ldr w9, [x7, #SNOOP_CTRL_REG]
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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#endif
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.endm
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#endif /* __MARVELL_MACROS_S__ */
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