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42a293379e
Some of COMPHY parameters depends on the hw connection between the SoC and the PHY, which can vary on different boards e.g. due to different wires length. Define the "porting layer" with some defaults parameters. It ease updating static values which needs to be updated due to board differences, which are now grouped in one place. Example porting layer for a8k-db is under: plat/marvell/a8k/a80x0/board/phy-porting-layer.h If for some boards parameters are not defined (missing phy-porting-layer.h), the default values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the following compilation warning is show: "Using default comphy params - you may need to suit them to your board". The common COMPHY driver code is extracted in order to be shared with future COMPHY driver for A3700 SoC platforms Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
156 lines
4.6 KiB
C
156 lines
4.6 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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/* Marvell CP110 ana A3700 common */
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#ifndef _PHY_COMPHY_COMMON_H
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#define _PHY_COMPHY_COMMON_H
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/* #define DEBUG_COMPHY */
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#ifdef DEBUG_COMPHY
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#define debug(format...) printf(format)
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#else
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#define debug(format, arg...)
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#endif
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/* A lane is described by 4 fields:
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* - bit 1~0 represent comphy polarity invert
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* - bit 7~2 represent comphy speed
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* - bit 11~8 represent unit index
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* - bit 16~12 represent mode
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* - bit 17 represent comphy indication of clock source
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* - bit 19-18 represents pcie width (in case of pcie comphy config.)
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* - bit 31~20 reserved
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*/
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#define COMPHY_INVERT_OFFSET 0
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#define COMPHY_INVERT_LEN 2
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#define COMPHY_INVERT_MASK COMPHY_MASK(COMPHY_INVERT_OFFSET, \
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COMPHY_INVERT_LEN)
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#define COMPHY_SPEED_OFFSET (COMPHY_INVERT_OFFSET + COMPHY_INVERT_LEN)
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#define COMPHY_SPEED_LEN 6
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#define COMPHY_SPEED_MASK COMPHY_MASK(COMPHY_SPEED_OFFSET, \
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COMPHY_SPEED_LEN)
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#define COMPHY_UNIT_ID_OFFSET (COMPHY_SPEED_OFFSET + COMPHY_SPEED_LEN)
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#define COMPHY_UNIT_ID_LEN 4
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#define COMPHY_UNIT_ID_MASK COMPHY_MASK(COMPHY_UNIT_ID_OFFSET, \
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COMPHY_UNIT_ID_LEN)
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#define COMPHY_MODE_OFFSET (COMPHY_UNIT_ID_OFFSET + COMPHY_UNIT_ID_LEN)
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#define COMPHY_MODE_LEN 5
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#define COMPHY_MODE_MASK COMPHY_MASK(COMPHY_MODE_OFFSET, COMPHY_MODE_LEN)
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#define COMPHY_CLK_SRC_OFFSET (COMPHY_MODE_OFFSET + COMPHY_MODE_LEN)
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#define COMPHY_CLK_SRC_LEN 1
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#define COMPHY_CLK_SRC_MASK COMPHY_MASK(COMPHY_CLK_SRC_OFFSET, \
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COMPHY_CLK_SRC_LEN)
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#define COMPHY_PCI_WIDTH_OFFSET (COMPHY_CLK_SRC_OFFSET + COMPHY_CLK_SRC_LEN)
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#define COMPHY_PCI_WIDTH_LEN 3
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#define COMPHY_PCI_WIDTH_MASK COMPHY_MASK(COMPHY_PCI_WIDTH_OFFSET, \
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COMPHY_PCI_WIDTH_LEN)
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#define COMPHY_MASK(offset, len) (((1 << (len)) - 1) << (offset))
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/* Macro which extracts mode from lane description */
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#define COMPHY_GET_MODE(x) (((x) & COMPHY_MODE_MASK) >> \
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COMPHY_MODE_OFFSET)
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/* Macro which extracts unit index from lane description */
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#define COMPHY_GET_ID(x) (((x) & COMPHY_UNIT_ID_MASK) >> \
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COMPHY_UNIT_ID_OFFSET)
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/* Macro which extracts speed from lane description */
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#define COMPHY_GET_SPEED(x) (((x) & COMPHY_SPEED_MASK) >> \
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COMPHY_SPEED_OFFSET)
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/* Macro which extracts clock source indication from lane description */
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#define COMPHY_GET_CLK_SRC(x) (((x) & COMPHY_CLK_SRC_MASK) >> \
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COMPHY_CLK_SRC_OFFSET)
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/* Macro which extracts pcie width indication from lane description */
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#define COMPHY_GET_PCIE_WIDTH(x) (((x) & COMPHY_PCI_WIDTH_MASK) >> \
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COMPHY_PCI_WIDTH_OFFSET)
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/* Macro which extracts the polarity invert from lane description */
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#define COMPHY_GET_POLARITY_INVERT(x) (((x) & COMPHY_INVERT_MASK) >> \
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COMPHY_INVERT_OFFSET)
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#define COMPHY_SATA_MODE 0x1
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#define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */
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#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */
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#define COMPHY_USB3H_MODE 0x4
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#define COMPHY_USB3D_MODE 0x5
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#define COMPHY_PCIE_MODE 0x6
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#define COMPHY_RXAUI_MODE 0x7
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#define COMPHY_XFI_MODE 0x8
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#define COMPHY_SFI_MODE 0x9
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#define COMPHY_USB3_MODE 0xa
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#define COMPHY_AP_MODE 0xb
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#define COMPHY_UNUSED 0xFFFFFFFF
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/* Polarity invert macro */
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#define COMPHY_POLARITY_NO_INVERT 0
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#define COMPHY_POLARITY_TXD_INVERT 1
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#define COMPHY_POLARITY_RXD_INVERT 2
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#define COMPHY_POLARITY_ALL_INVERT (COMPHY_POLARITY_TXD_INVERT | \
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COMPHY_POLARITY_RXD_INVERT)
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enum reg_width_type {
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REG_16BIT = 0,
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REG_32BIT,
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};
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enum {
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COMPHY_LANE0 = 0,
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COMPHY_LANE1,
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COMPHY_LANE2,
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COMPHY_LANE3,
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COMPHY_LANE4,
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COMPHY_LANE5,
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COMPHY_LANE_MAX,
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};
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static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val,
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uint32_t mask,
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uint32_t usec_timeout,
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enum reg_width_type type)
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{
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uint32_t data;
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do {
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udelay(1);
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if (type == REG_16BIT)
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data = mmio_read_16(addr) & mask;
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else
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data = mmio_read_32(addr) & mask;
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} while (data != val && --usec_timeout > 0);
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if (usec_timeout == 0)
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return data;
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return 0;
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}
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static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask)
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{
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debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ",
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addr, data, mask);
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debug("old value = 0x%x ==> ", mmio_read_32(addr));
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mmio_clrsetbits_32(addr, mask, data);
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debug("new val 0x%x\n", mmio_read_32(addr));
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}
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static inline void __unused reg_set16(uintptr_t addr, uint16_t data,
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uint16_t mask)
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{
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debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ",
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addr, data, mask);
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debug("old value = 0x%x ==> ", mmio_read_16(addr));
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mmio_clrsetbits_16(addr, mask, data);
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debug("new val 0x%x\n", mmio_read_16(addr));
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}
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#endif /* _PHY_COMPHY_COMMON_H */
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