mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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204d5e67b9
- Develop SiPSVC-V3 framework to support async/yielding SMC calls. - Add support for multi clients with multiple jobs running together. - Add support for SDM doorbell interrupt handling. - Keep the framework backward compatible with V1 clients. - Enable the framework on all the platform Agilex7, Agilex5, N5X, and Stratix10. Change-Id: I9eb61c48be89867b4227e084493bfcf67cbe7924 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@altera.com>
405 lines
13 KiB
C
405 lines
13 KiB
C
/*
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_MBOX_H
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#define SOCFPGA_MBOX_H
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#include <lib/utils_def.h>
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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#define MBOX_OFFSET 0x10a30000
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#else
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#define MBOX_OFFSET 0xffa30000
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#endif
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#define MBOX_ATF_CLIENT_ID 0x1U
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#define MBOX_MAX_JOB_ID 0xFU
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#define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U)
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#define MBOX_JOB_ID MBOX_MAX_JOB_ID
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#define MBOX_TEST_BIT BIT(31)
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/* Mailbox Shared Memory Register Map */
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#define MBOX_CIN 0x00 /* Command valid offset, to SDM */
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#define MBOX_ROUT 0x04 /* Response output offset, to SDM */
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#define MBOX_URG 0x08 /* Urgent command, to SDM */
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#define MBOX_INT 0x0C /* Interrupt enables, to SDM */
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/* 0x10 - 0x1F, Reserved */
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#define MBOX_COUT 0x20 /* Command free offset, from SDM */
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#define MBOX_RIN 0x24 /* Response valid offset, from SDM */
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#define MBOX_STATUS 0x2C /* Mailbox status from SDM to client */
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/* 0x30 - 0x3F, Reserved */
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#define MBOX_CMD_BUFFER 0x40 /* Circular buffer, cmds to SDM */
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#define MBOX_RESP_BUFFER 0xC0 /* Circular buffer, resp from SDM */
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#define MBOX_DOORBELL_TO_SDM 0x400 /* Doorbell from HPS to SDM */
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#define MBOX_DOORBELL_FROM_SDM 0x480 /* Doorbell from SDM to HPS */
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/* Mailbox commands */
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#define MBOX_CMD_NOOP 0x00
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#define MBOX_CMD_SYNC 0x01
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#define MBOX_CMD_RESTART 0x02
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#define MBOX_CMD_CANCEL 0x03
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#define MBOX_CMD_VAB_SRC_CERT 0x0B
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#define MBOX_CMD_GET_IDCODE 0x10
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#define MBOX_CMD_GET_USERCODE 0x13
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#define MBOX_CMD_GET_CHIPID 0x12
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#define MBOX_CMD_FPGA_CONFIG_COMP 0x45
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#define MBOX_CMD_REBOOT_HPS 0x47
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/* Reconfiguration Commands */
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#define MBOX_CONFIG_STATUS 0x04
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#define MBOX_RECONFIG 0x06
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#define MBOX_RECONFIG_DATA 0x08
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#define MBOX_RECONFIG_STATUS 0x09
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/* HWMON Commands */
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#define MBOX_HWMON_READVOLT 0x18
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#define MBOX_HWMON_READTEMP 0x19
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/* QSPI Commands */
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#define MBOX_CMD_QSPI_OPEN 0x32
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#define MBOX_CMD_QSPI_CLOSE 0x33
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#define MBOX_CMD_QSPI_SET_CS 0x34
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#define MBOX_CMD_QSPI_ERASE 0x38
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#define MBOX_CMD_QSPI_WRITE 0x39
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#define MBOX_CMD_QSPI_READ 0x3A
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#define MBOX_CMD_QSPI_DIRECT 0x3B
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#define MBOX_CMD_QSPI_GET_DEV_INFO 0x74
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/* SEU Commands */
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#define MBOX_CMD_SEU_ERR_READ 0x3C
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#define MBOX_CMD_SAFE_INJECT_SEU_ERR 0x41
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/* RSU Commands */
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#define MBOX_GET_SUBPARTITION_TABLE 0x5A
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#define MBOX_RSU_STATUS 0x5B
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#define MBOX_RSU_UPDATE 0x5C
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#define MBOX_HPS_STAGE_NOTIFY 0x5D
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#define MBOX_RSU_GET_DEVICE_INFO 0x74
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/* FCS Command */
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#define MBOX_FCS_GET_PROVISION 0x7B
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#define MBOX_FCS_CNTR_SET_PREAUTH 0x7C
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#define MBOX_FCS_ENCRYPT_REQ 0x7E
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#define MBOX_FCS_DECRYPT_REQ 0x7F
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#define MBOX_FCS_RANDOM_GEN 0x80
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#define MBOX_FCS_AES_CRYPT_REQ 0x81
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#define MBOX_FCS_GET_DIGEST_REQ 0x82
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#define MBOX_FCS_MAC_VERIFY_REQ 0x83
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#define MBOX_FCS_ECDSA_HASH_SIGN_REQ 0x84
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#define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ 0x85
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#define MBOX_FCS_ECDSA_HASH_SIG_VERIFY 0x86
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#define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY 0x87
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#define MBOX_FCS_ECDSA_GET_PUBKEY 0x88
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#define MBOX_FCS_ECDH_REQUEST 0x89
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#define MBOX_FCS_HKDF_REQUEST 0x8B
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#define MBOX_FCS_OPEN_CS_SESSION 0xA0
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#define MBOX_FCS_CLOSE_CS_SESSION 0xA1
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#define MBOX_FCS_IMPORT_CS_KEY 0xA5
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#define MBOX_FCS_EXPORT_CS_KEY 0xA6
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#define MBOX_FCS_REMOVE_CS_KEY 0xA7
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#define MBOX_FCS_GET_CS_KEY_INFO 0xA8
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#define MBOX_FCS_CREATE_CS_KEY 0xA9
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/* PSG SIGMA Commands */
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#define MBOX_PSG_SIGMA_TEARDOWN 0xD5
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/* Attestation Commands */
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#define MBOX_CREATE_CERT_ON_RELOAD 0x180
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#define MBOX_GET_ATTESTATION_CERT 0x181
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#define MBOX_ATTESTATION_SUBKEY 0x182
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#define MBOX_GET_MEASUREMENT 0x183
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/* Miscellaneous commands */
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#define MBOX_CMD_MCTP_MSG 0x194
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#define MBOX_GET_ROM_PATCH_SHA384 0x1B0
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#define MBOX_CMD_GET_DEVICEID 0x500
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/* Mailbox Definitions */
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#define CMD_DIRECT 0
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#define CMD_INDIRECT 1
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#define CMD_CASUAL 0
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#define CMD_URGENT 1
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/* Mailbox command flags and related macros */
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#define MBOX_CMD_FLAG_DIRECT BIT(0)
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#define MBOX_CMD_FLAG_INDIRECT BIT(1)
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#define MBOX_CMD_FLAG_CASUAL BIT(2)
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#define MBOX_CMD_FLAG_URGENT BIT(3)
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#define MBOX_CMD_FLAG_CASUAL_INDIRECT (MBOX_CMD_FLAG_CASUAL | \
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MBOX_CMD_FLAG_INDIRECT)
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#define IS_CMD_SET(cmd, _type) ((((cmd) & MBOX_CMD_FLAG_##_type) != 0) ? \
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1 : 0)
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#define MBOX_WORD_BYTE 4U
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#define MBOX_RESP_BUFFER_SIZE 16
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#define MBOX_CMD_BUFFER_SIZE 32
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#define MBOX_INC_HEADER_MAX_WORD_SIZE 1024U
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/* Execution states for HPS_STAGE_NOTIFY */
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#define HPS_EXECUTION_STATE_FSBL 0
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#define HPS_EXECUTION_STATE_SSBL 1
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#define HPS_EXECUTION_STATE_OS 2
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/* Status Response */
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#define MBOX_RET_OK 0
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#define MBOX_RET_ERROR -1
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#define MBOX_NO_RESPONSE -2
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#define MBOX_WRONG_ID -3
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#define MBOX_BUFFER_FULL -4
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#define MBOX_BUSY -5
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#define MBOX_TIMEOUT -2047
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/* Key Status */
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#define MBOX_RET_SDOS_DECRYPTION_ERROR_102 -258
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#define MBOX_RET_SDOS_DECRYPTION_ERROR_103 -259
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/* Reconfig Status Response */
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#define RECONFIG_STATUS_STATE 0
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#define RECONFIG_STATUS_PIN_STATUS 2
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#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
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#define PIN_STATUS_NSTATUS (U(1) << 31)
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#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3)
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#define SOFTFUNC_STATUS_INIT_DONE (1 << 1)
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#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)
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#define MBOX_CFGSTAT_STATE_IDLE 0x00000000
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#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
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#define MBOX_CFGSTAT_VAB_BS_PREAUTH 0x20000000
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#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
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#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001
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#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002
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#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003
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#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004
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#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005
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#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006
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#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
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#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
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/* Mailbox Macros */
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#define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \
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+ MBOX_WORD_BYTE * (ptr))
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/* Mailbox interrupt flags and masks */
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#define MBOX_INT_FLAG_COE BIT(0) /* COUT update interrupt enable */
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#define MBOX_INT_FLAG_RIE BIT(1) /* RIN update interrupt enable */
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#define MBOX_INT_FLAG_UAE BIT(8) /* Urgent ACK interrupt enable */
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#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & MBOX_INT_FLAG_COE)
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#define MBOX_RIE_BIT(INTERRUPT) ((INTERRUPT) & MBOX_INT_FLAG_RIE)
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#define MBOX_UAE_BIT(INTERRUPT) ((INTERRUPT) & MBOX_INT_FLAG_UAE)
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/* Mailbox response and status */
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#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x000007ff)
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#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
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#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
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#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
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#define MBOX_RESP_TRANSACTION_ID(BUFFER) (((BUFFER) & 0xff000000) >> 24)
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#define MBOX_STATUS_UA_MASK (1<<8)
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/* Mailbox command and response */
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#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
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#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID << 24)
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#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
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#define MBOX_INDIRECT(val) ((val) << 11)
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#define MBOX_CMD_MASK(header) ((header) & 0x7ff)
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/* Mailbox payload */
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#define MBOX_DATA_MAX_LEN 0x3ff
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#define MBOX_PAYLOAD_FLAG_BUSY BIT(0)
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/* RSU Macros */
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#define RSU_VERSION_ACMF BIT(8)
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#define RSU_VERSION_ACMF_MASK 0xff00
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/* Config Status Macros */
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#define CONFIG_STATUS_WORD_SIZE 16U
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#define CONFIG_STATUS_FW_VER_OFFSET 1
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#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF
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/* QSPI mailbox command macros */
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#define MBOX_QSPI_SET_CS_OFFSET (28)
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#define MBOX_QSPI_SET_CS_MODE_OFFSET (27)
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#define MBOX_QSPI_SET_CS_CA_OFFSET (26)
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#define MBOX_QSPI_ERASE_SIZE_GRAN (0x400)
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#define MBOX_4K_ALIGNED_MASK (0xFFF)
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#define MBOX_IS_4K_ALIGNED(x) ((x) & MBOX_4K_ALIGNED_MASK)
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#define MBOX_IS_WORD_ALIGNED(x) (!((x) & 0x3))
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#define MBOX_QSPI_RW_MAX_WORDS (0x1000)
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/* Data structure */
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typedef struct mailbox_payload {
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uint32_t header;
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uint32_t data[MBOX_DATA_MAX_LEN];
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} mailbox_payload_t;
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typedef struct mailbox_container {
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uint32_t flag;
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uint32_t index;
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mailbox_payload_t *payload;
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} mailbox_container_t;
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/* Mailbox Function Definitions */
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void mailbox_set_int(uint32_t interrupt_input);
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int mailbox_init(void);
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void mailbox_set_qspi_close(void);
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void mailbox_hps_qspi_enable(void);
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int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args,
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unsigned int len, uint32_t urgent, uint32_t *response,
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unsigned int *resp_len);
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int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args,
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unsigned int len, unsigned int indirect);
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int mailbox_send_cmd_async_ext(uint32_t header_cmd, uint32_t *args,
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unsigned int len);
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int mailbox_read_response(uint32_t *job_id, uint32_t *response,
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unsigned int *resp_len);
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int mailbox_read_response_async(uint32_t *job_id, uint32_t *header,
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uint32_t *response, unsigned int *resp_len,
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uint8_t ignore_client_id);
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int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
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unsigned int *resp_len);
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void mailbox_reset_cold(void);
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void mailbox_reset_warm(uint32_t reset_type);
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void mailbox_clear_response(void);
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int intel_mailbox_get_config_status(uint32_t cmd, bool init_done,
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uint32_t *err_states);
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int intel_mailbox_is_fpga_not_ready(void);
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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void intel_smmu_hps_remapper_init(uint64_t *mem);
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int intel_smmu_hps_remapper_config(uint32_t remapper_bypass);
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#endif
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int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_get_device_info(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_update(uint32_t *flash_offset);
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int mailbox_hps_stage_notify(uint32_t execution_stage);
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int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf);
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int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf);
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int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len);
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int mailbox_send_fpga_config_comp(void);
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#if SIP_SVC_V3
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#define MBOX_CLIENT_ID_SHIFT (28)
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#define MBOX_JOB_ID_SHIFT (24)
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#define MBOX_CMD_LEN_SHIFT (12)
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#define MBOX_INDIRECT_SHIFT (11)
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#define MBOX_FRAME_CMD_HEADER(client_id, job_id, args_len, indirect, cmd)\
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((client_id << MBOX_CLIENT_ID_SHIFT) | \
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(job_id << MBOX_JOB_ID_SHIFT) | \
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(args_len << MBOX_CMD_LEN_SHIFT) | \
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(indirect << MBOX_CMD_LEN_SHIFT) | \
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cmd)
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#define FLAG_SDM_RESPONSE_IS_VALID BIT(0)
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#define FLAG_SDM_RESPONSE_IS_USED BIT(1)
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#define FLAG_SDM_RESPONSE_IS_IN_PROGRESS BIT(2)
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#define FLAG_SDM_RESPONSE_IS_POLL_ON_INTR BIT(3)
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/*
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* TODO: Re-visit this queue size based on the system load.
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* 4 bits for client ID and 4 bits for job ID, total 8 bits and we can have up to
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* 256 transactions. We can tune this based on our system load at any given time
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*/
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#define MBOX_SVC_CMD_QUEUE_SIZE (32)
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#define MBOX_SVC_RESP_QUEUE_SIZE (32)
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#define MBOX_SVC_MAX_JOB_ID (16)
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#define MBOX_SVC_CMD_ARG_SIZE (2)
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#define MBOX_SVC_CMD_IS_USED BIT(0)
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#define MBOX_SVC_CMD_CB_ARGS_SIZE (4)
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#define MBOX_SVC_MAX_CLIENTS (16)
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#define MBOX_SVC_MAX_RESP_DATA_SIZE (32)
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#define MBOX_SVC_SMC_RET_MAX_SIZE (8)
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/* Client ID(4bits) + Job ID(4bits) = Transcation ID(TID - 8bits, 256 combinations) */
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#define MBOX_MAX_TIDS (256)
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/* Each transcation ID bitmap holds 64bits */
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#define MBOX_TID_BITMAP_SIZE (sizeof(uint64_t) * 8)
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/* Number of transcation ID bitmaps required to hold 256 combinations */
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#define MBOX_MAX_TIDS_BITMAP (MBOX_MAX_TIDS / MBOX_TID_BITMAP_SIZE)
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/* SDM Response State (SRS) enums */
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typedef enum sdm_resp_state {
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SRS_WAIT_FOR_RESP = 0x00U,
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SRS_WAIT_FOR_HEADER,
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SRS_WAIT_FOR_ARGUMENTS,
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SRS_SYNC_ERROR
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} sdm_resp_state_t;
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/* SDM response data structure */
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typedef struct sdm_response {
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bool is_poll_intr;
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uint8_t client_id;
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uint8_t job_id;
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uint16_t resp_len;
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uint16_t err_code;
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uint32_t flags;
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uint32_t header;
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uint16_t rcvd_resp_len;
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uint32_t resp_data[MBOX_SVC_MAX_RESP_DATA_SIZE];
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} sdm_response_t;
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/* SDM client callback template */
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typedef uint8_t (*sdm_command_callback)(void *resp, void *cmd,
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uint32_t *ret_args);
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/* SDM command data structure */
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typedef struct sdm_command {
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uint8_t client_id;
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uint8_t job_id;
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uint32_t flags;
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sdm_command_callback cb;
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uint32_t *cb_args;
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uint8_t cb_args_len;
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} sdm_command_t;
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/* Get the transcation ID from client ID and job ID. */
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#define MBOX_GET_TRANS_ID(cid, jib) (((cid) << 4) | (jib))
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/* Mailbox service data structure */
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typedef struct mailbox_service {
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sdm_resp_state_t resp_state;
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sdm_resp_state_t next_resp_state;
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uint32_t flags;
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int curr_di;
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uint64_t received_bitmap[MBOX_MAX_TIDS_BITMAP];
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uint64_t interrupt_bitmap[MBOX_MAX_TIDS_BITMAP];
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sdm_command_t cmd_queue[MBOX_SVC_CMD_QUEUE_SIZE];
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sdm_response_t resp_queue[MBOX_SVC_RESP_QUEUE_SIZE];
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} mailbox_service_t;
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int mailbox_send_cmd_async_v3(uint8_t client_id, uint8_t job_id, uint32_t cmd,
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uint32_t *args, uint32_t args_len, uint8_t cmd_flag,
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sdm_command_callback cb, uint32_t *cb_args,
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uint32_t cb_args_len);
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int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint32_t *ret_args,
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uint32_t *ret_args_size);
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int mailbox_response_poll_on_intr_v3(uint8_t *client_id, uint8_t *job_id,
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uint64_t *bitmap);
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#endif /* #if SIP_SVC_V3 */
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#endif /* SOCFPGA_MBOX_H */
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