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https://github.com/ARM-software/arm-trusted-firmware.git
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e81e999b9d
Implements the loop workaround for Cortex-X1. Signed-off-by: Okash Khawaja <okash@google.com> Change-Id: I5828a26c1ec3cfb718246ea5c3b099dabc0fb3d7
217 lines
5.3 KiB
ArmAsm
217 lines
5.3 KiB
ArmAsm
/*
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* Copyright (c) 2022, Google LLC. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <cortex_x1.h>
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#include <cpu_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* --------------------------------------------------
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* Errata Workaround for X1 Erratum 1821534.
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* This applies to revision r0p0 and r1p0 of X1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_x1_1821534_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1821534
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cbz x0, 1f
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mrs x1, CORTEX_X1_ACTLR2_EL1
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orr x1, x1, BIT(2)
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msr CORTEX_X1_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_x1_1821534_wa
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func check_errata_1821534
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1821534
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/* --------------------------------------------------
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* Errata Workaround for X1 Erratum 1688305.
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* This applies to revision r0p0 and r1p0 of X1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_x1_1688305_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1688305
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cbz x0, 1f
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mrs x0, CORTEX_X1_ACTLR2_EL1
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orr x0, x0, BIT(1)
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msr CORTEX_X1_ACTLR2_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_x1_1688305_wa
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func check_errata_1688305
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1688305
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/* --------------------------------------------------
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* Errata Workaround for X1 Erratum 1827429.
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* This applies to revision r0p0 and r1p0 of X1.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_x1_1827429_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1827429
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cbz x0, 1f
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mrs x0, CORTEX_X1_CPUECTLR_EL1
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orr x0, x0, BIT(53)
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msr CORTEX_X1_CPUECTLR_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_x1_1827429_wa
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func check_errata_1827429
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1827429
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-X1.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func cortex_x1_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_X1_1821534
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mov x0, x18
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bl errata_x1_1821534_wa
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#endif
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#if ERRATA_X1_1688305
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mov x0, x18
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bl errata_x1_1688305_wa
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#endif
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#if ERRATA_X1_1827429
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mov x0, x18
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bl errata_x1_1827429_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-X1 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_x1
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret x19
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endfunc cortex_x1_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_x1_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_X1_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK
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msr CORTEX_X1_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_x1_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex X1. Must follow AAPCS.
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*/
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func cortex_x1_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_X1_1821534, cortex_x1, 1821534
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report_errata ERRATA_X1_1688305, cortex_x1, 1688305
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report_errata ERRATA_X1_1827429, cortex_x1, 1827429
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report_errata WORKAROUND_CVE_2022_23960, cortex_x1, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_x1_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides Cortex X1 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x1_regs, "aS"
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cortex_x1_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x1_cpu_reg_dump
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adr x6, cortex_x1_regs
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mrs x8, CORTEX_X1_CPUECTLR_EL1
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ret
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endfunc cortex_x1_cpu_reg_dump
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declare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \
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cortex_x1_reset_func, \
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cortex_x1_core_pwr_dwn
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