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e72bbe47ba
Cortex-A510 erratum 2041909 is a Cat B erratum that applies to revision r0p2 and is fixed in r0p3. It is also present in r0p0 and r0p1 but there is no workaround in these revisions. SDEN can be found here: https://developer.arm.com/documentation/SDEN2397239 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7b1498faa0c79488dee0d11d07f6e9f58144e298
251 lines
6.3 KiB
ArmAsm
251 lines
6.3 KiB
ArmAsm
/*
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* Copyright (c) 2022, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a510.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #1922240.
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* This applies only to revision r0p0 (fixed in r0p1)
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_1922240_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1922240
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cbz x0, 1f
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/* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */
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mrs x0, CORTEX_A510_CMPXACTLR_EL1
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mov x1, #3
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bfi x0, x1, #10, #2
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msr CORTEX_A510_CMPXACTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_1922240_wa
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func check_errata_1922240
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/* Applies to r0p0 only */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_1922240
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2288014.
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* This applies only to revisions r0p0, r0p1, r0p2,
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* r0p3 and r1p0. (fixed in r1p1)
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2288014_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2288014
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cbz x0, 1f
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/* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
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mrs x0, CORTEX_A510_CPUACTLR_EL1
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mov x1, #1
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bfi x0, x1, #18, #1
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msr CORTEX_A510_CPUACTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_2288014_wa
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func check_errata_2288014
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/* Applies to r1p0 and below */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_2288014
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2042739.
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* This applies only to revisions r0p0, r0p1 and r0p2.
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* (fixed in r0p3)
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2042739_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2042739
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cbz x0, 1f
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/* Apply the workaround by disabling ReadPreferUnique. */
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mrs x0, CORTEX_A510_CPUECTLR_EL1
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mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
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bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
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msr CORTEX_A510_CPUECTLR_EL1, x0
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1:
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ret x17
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endfunc errata_cortex_a510_2042739_wa
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func check_errata_2042739
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/* Applies to revisions r0p0 - r0p2 */
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mov x1, #0x02
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b cpu_rev_var_ls
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endfunc check_errata_2042739
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/* --------------------------------------------------
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* Errata Workaround for Cortex-A510 Errata #2041909.
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* This applies only to revision r0p2 and it is fixed in
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* r0p3. The issue is also present in r0p0 and r0p1 but
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* there is no workaround in those revisions.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1, x2, x17
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* --------------------------------------------------
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*/
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func errata_cortex_a510_2041909_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2041909
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cbz x0, 1f
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/* Apply workaround */
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mov x0, xzr
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msr S3_6_C15_C4_0, x0
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isb
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mov x0, #0x8500000
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msr S3_6_C15_C4_2, x0
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mov x0, #0x1F700000
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movk x0, #0x8, lsl #32
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msr S3_6_C15_C4_3, x0
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mov x0, #0x3F1
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movk x0, #0x110, lsl #16
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msr S3_6_C15_C4_1, x0
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isb
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1:
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ret x17
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endfunc errata_cortex_a510_2041909_wa
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func check_errata_2041909
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/* Applies only to revision r0p2 */
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mov x1, #0x02
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mov x2, #0x02
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b cpu_rev_var_range
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endfunc check_errata_2041909
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a510_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_A510_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A510_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a510_core_pwr_dwn
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/*
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* Errata printing function for Cortex-A510. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_a510_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A510_1922240, cortex_a510, 1922240
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report_errata ERRATA_A510_2288014, cortex_a510, 2288014
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report_errata ERRATA_A510_2042739, cortex_a510, 2042739
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report_errata ERRATA_A510_2041909, cortex_a510, 2041909
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a510_errata_report
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#endif
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func cortex_a510_reset_func
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mov x19, x30
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/* Disable speculative loads */
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msr SSBS, xzr
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isb
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/* Get the CPU revision and stash it in x18. */
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A510_1922240
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mov x0, x18
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bl errata_cortex_a510_1922240_wa
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#endif
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#if ERRATA_A510_2288014
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mov x0, x18
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bl errata_cortex_a510_2288014_wa
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#endif
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#if ERRATA_A510_2042739
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mov x0, x18
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bl errata_cortex_a510_2042739_wa
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#endif
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#if ERRATA_A510_2041909
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mov x0, x18
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bl errata_cortex_a510_2041909_wa
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#endif
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ret x19
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endfunc cortex_a510_reset_func
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/* ---------------------------------------------
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* This function provides Cortex-A510 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a510_regs, "aS"
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cortex_a510_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a510_cpu_reg_dump
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adr x6, cortex_a510_regs
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mrs x8, CORTEX_A510_CPUECTLR_EL1
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ret
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endfunc cortex_a510_cpu_reg_dump
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declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \
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cortex_a510_reset_func, \
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cortex_a510_core_pwr_dwn
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