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e6e1d0ac16
The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are added to the Cortex-A76 cpu specific file. The workarounds are disabled by default and have to be explicitly enabled by the platform integrator. Change-Id: I70474927374cb67725f829d159ddde9ac4edc343 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A76_H
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#define CORTEX_A76_H
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#include <lib/utils_def.h>
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/* Cortex-A76 MIDR for revision 0 */
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#define CORTEX_A76_MIDR U(0x410fd0b0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A76_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A76_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)
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#define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A76_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)
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#define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
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#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
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#define CORTEX_A76_CPUACTLR3_EL1 S3_0_C15_C1_2
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#define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
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/* Definitions of register field mask in CORTEX_A76_CPUPWRCTLR_EL1 */
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#define CORTEX_A76_CORE_PWRDN_EN_MASK U(0x1)
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#endif /* CORTEX_A76_H */
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