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e61713b007
scr_el3 registers cannot be modified in lower ELs which means it retains
the same value which is stored in the EL3 cpu context structure for the
given world. So, we should not save the register when entering to EL3
from lower EL as we have the copy of it present in cpu context.
During EL3 execution SCR_EL3 value can be modifed for following cases
1. Changes which is required for EL3 execution, this change is temp
and do not need to be saved.
2. Changes which affects lower EL execution, these changes need to be
written to cpu context as well and will be retrieved when scr_el3
is restored as part of exiting EL3
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I9cc984ddf50e27d09e361bd83b1b3c9f068cf2fd
632 lines
18 KiB
ArmAsm
632 lines
18 KiB
ArmAsm
/*
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* Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl31/ea_handle.h>
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#include <bl31/interrupt_mgmt.h>
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#include <common/runtime_svc.h>
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#include <context.h>
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#include <el3_common_macros.S>
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#include <lib/el3_runtime/cpu_data.h>
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#include <lib/smccc.h>
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.globl runtime_exceptions
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.globl sync_exception_sp_el0
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.globl irq_sp_el0
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.globl fiq_sp_el0
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.globl serror_sp_el0
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.globl sync_exception_sp_elx
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.globl irq_sp_elx
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.globl fiq_sp_elx
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.globl serror_sp_elx
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.globl sync_exception_aarch64
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.globl irq_aarch64
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.globl fiq_aarch64
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.globl serror_aarch64
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.globl sync_exception_aarch32
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.globl irq_aarch32
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.globl fiq_aarch32
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.globl serror_aarch32
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/*
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* Macro that prepares entry to EL3 upon taking an exception.
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*
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* With RAS_EXTENSION, this macro synchronizes pending errors with an ESB
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* instruction. When an error is thus synchronized, the handling is
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* delegated to platform EA handler.
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*
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* Without RAS_EXTENSION, this macro synchronizes pending errors using
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* a DSB, unmasks Asynchronous External Aborts and saves X30 before
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* setting the flag CTX_IS_IN_EL3.
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*/
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.macro check_and_unmask_ea
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#if RAS_EXTENSION
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/* Synchronize pending External Aborts */
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esb
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/* Unmask the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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/*
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* Explicitly save x30 so as to free up a register and to enable
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* branching
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*/
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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/* Check for SErrors synchronized by the ESB instruction */
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mrs x30, DISR_EL1
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tbz x30, #DISR_A_BIT, 1f
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/*
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
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* Also set the PSTATE to a known state.
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*/
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bl prepare_el3_entry
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bl handle_lower_el_ea_esb
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/* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */
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bl restore_gp_pmcr_pauth_regs
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1:
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#else
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/*
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* For SoCs which do not implement RAS, use DSB as a barrier to
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* synchronize pending external aborts.
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*/
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dsb sy
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/* Unmask the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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/* Use ISB for the above unmask operation to take effect immediately */
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isb
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/*
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* Refer Note 1. No need to restore X30 as both handle_sync_exception
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* and handle_interrupt_exception macro which follow this macro modify
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* X30 anyway.
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*/
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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mov x30, #1
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str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
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dmb sy
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#endif
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.endm
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#if !RAS_EXTENSION
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/*
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* Note 1: The explicit DSB at the entry of various exception vectors
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* for handling exceptions from lower ELs can inadvertently trigger an
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* SError exception in EL3 due to pending asynchronous aborts in lower
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* ELs. This will end up being handled by serror_sp_elx which will
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* ultimately panic and die.
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* The way to workaround is to update a flag to indicate if the exception
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* truly came from EL3. This flag is allocated in the cpu_context
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* structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3"
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* This is not a bullet proof solution to the problem at hand because
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* we assume the instructions following "isb" that help to update the
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* flag execute without causing further exceptions.
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*/
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/* ---------------------------------------------------------------------
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* This macro handles Asynchronous External Aborts.
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* ---------------------------------------------------------------------
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*/
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.macro handle_async_ea
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/*
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* Use a barrier to synchronize pending external aborts.
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*/
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dsb sy
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/* Unmask the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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/* Use ISB for the above unmask operation to take effect immediately */
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isb
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/* Refer Note 1 */
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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mov x30, #1
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str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
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dmb sy
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b handle_lower_el_async_ea
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.endm
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/*
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* This macro checks if the exception was taken due to SError in EL3 or
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* because of pending asynchronous external aborts from lower EL that got
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* triggered due to explicit synchronization in EL3. Refer Note 1.
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*/
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.macro check_if_serror_from_EL3
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/* Assumes SP_EL3 on entry */
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str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
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cbnz x30, exp_from_EL3
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/* Handle asynchronous external abort from lower EL */
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b handle_lower_el_async_ea
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exp_from_EL3:
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/* Jump to plat_handle_el3_ea which does not return */
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.endm
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#endif
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/* ---------------------------------------------------------------------
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* This macro handles Synchronous exceptions.
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* Only SMC exceptions are supported.
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* ---------------------------------------------------------------------
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*/
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.macro handle_sync_exception
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#if ENABLE_RUNTIME_INSTRUMENTATION
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/*
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* Read the timestamp value and store it in per-cpu data. The value
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* will be extracted from per-cpu data by the C level SMC handler and
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* saved to the PMF timestamp region.
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*/
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mrs x30, cntpct_el0
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str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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mrs x29, tpidr_el3
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str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
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ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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#endif
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mrs x30, esr_el3
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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/* Handle SMC exceptions separately from other synchronous exceptions */
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cmp x30, #EC_AARCH32_SMC
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b.eq smc_handler32
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cmp x30, #EC_AARCH64_SMC
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b.eq smc_handler64
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/* Synchronous exceptions other than the above are assumed to be EA */
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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b enter_lower_el_sync_ea
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.endm
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/* ---------------------------------------------------------------------
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* This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
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* interrupts.
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* ---------------------------------------------------------------------
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*/
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.macro handle_interrupt_exception label
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/*
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
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* Also set the PSTATE to a known state.
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*/
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bl prepare_el3_entry
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#if ENABLE_PAUTH
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/* Load and program APIAKey firmware key */
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bl pauth_load_bl31_apiakey
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#endif
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/* Save the EL3 system registers needed to return from this exception */
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mrs x0, spsr_el3
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mrs x1, elr_el3
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stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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/* Switch to the runtime stack i.e. SP_EL0 */
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ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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mov x20, sp
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msr spsel, #MODE_SP_EL0
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mov sp, x2
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/*
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* Find out whether this is a valid interrupt type.
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* If the interrupt controller reports a spurious interrupt then return
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* to where we came from.
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*/
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bl plat_ic_get_pending_interrupt_type
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cmp x0, #INTR_TYPE_INVAL
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b.eq interrupt_exit_\label
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/*
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* Get the registered handler for this interrupt type.
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* A NULL return value could be 'cause of the following conditions:
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*
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* a. An interrupt of a type was routed correctly but a handler for its
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* type was not registered.
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*
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* b. An interrupt of a type was not routed correctly so a handler for
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* its type was not registered.
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*
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* c. An interrupt of a type was routed correctly to EL3, but was
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* deasserted before its pending state could be read. Another
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* interrupt of a different type pended at the same time and its
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* type was reported as pending instead. However, a handler for this
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* type was not registered.
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*
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* a. and b. can only happen due to a programming error. The
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* occurrence of c. could be beyond the control of Trusted Firmware.
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* It makes sense to return from this exception instead of reporting an
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* error.
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*/
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bl get_interrupt_type_handler
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cbz x0, interrupt_exit_\label
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mov x21, x0
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mov x0, #INTR_ID_UNAVAILABLE
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/* Set the current security state in the 'flags' parameter */
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mrs x2, scr_el3
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ubfx x1, x2, #0, #1
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/* Restore the reference to the 'handle' i.e. SP_EL3 */
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mov x2, x20
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/* x3 will point to a cookie (not used now) */
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mov x3, xzr
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/* Call the interrupt type handler */
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blr x21
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interrupt_exit_\label:
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/* Return from exception, possibly in a different security state */
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b el3_exit
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.endm
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vector_base runtime_exceptions
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/* ---------------------------------------------------------------------
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* Current EL with SP_EL0 : 0x0 - 0x200
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* ---------------------------------------------------------------------
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*/
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vector_entry sync_exception_sp_el0
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#ifdef MONITOR_TRAPS
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stp x29, x30, [sp, #-16]!
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mrs x30, esr_el3
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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/* Check for BRK */
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cmp x30, #EC_BRK
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b.eq brk_handler
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ldp x29, x30, [sp], #16
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#endif /* MONITOR_TRAPS */
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/* We don't expect any synchronous exceptions from EL3 */
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b report_unhandled_exception
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end_vector_entry sync_exception_sp_el0
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vector_entry irq_sp_el0
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/*
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* EL3 code is non-reentrant. Any asynchronous exception is a serious
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* error. Loop infinitely.
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*/
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b report_unhandled_interrupt
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end_vector_entry irq_sp_el0
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vector_entry fiq_sp_el0
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b report_unhandled_interrupt
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end_vector_entry fiq_sp_el0
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vector_entry serror_sp_el0
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no_ret plat_handle_el3_ea
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end_vector_entry serror_sp_el0
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/* ---------------------------------------------------------------------
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* Current EL with SP_ELx: 0x200 - 0x400
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* ---------------------------------------------------------------------
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*/
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vector_entry sync_exception_sp_elx
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/*
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* This exception will trigger if anything went wrong during a previous
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* exception entry or exit or while handling an earlier unexpected
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* synchronous exception. There is a high probability that SP_EL3 is
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* corrupted.
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*/
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b report_unhandled_exception
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end_vector_entry sync_exception_sp_elx
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vector_entry irq_sp_elx
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b report_unhandled_interrupt
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end_vector_entry irq_sp_elx
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vector_entry fiq_sp_elx
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b report_unhandled_interrupt
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end_vector_entry fiq_sp_elx
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vector_entry serror_sp_elx
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#if !RAS_EXTENSION
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check_if_serror_from_EL3
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#endif
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no_ret plat_handle_el3_ea
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end_vector_entry serror_sp_elx
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/* ---------------------------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* ---------------------------------------------------------------------
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*/
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vector_entry sync_exception_aarch64
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/*
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* This exception vector will be the entry point for SMCs and traps
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* that are unhandled at lower ELs most commonly. SP_EL3 should point
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* to a valid cpu context where the general purpose and system register
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* state can be saved.
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*/
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_sync_exception
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end_vector_entry sync_exception_aarch64
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vector_entry irq_aarch64
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_interrupt_exception irq_aarch64
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end_vector_entry irq_aarch64
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vector_entry fiq_aarch64
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_interrupt_exception fiq_aarch64
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end_vector_entry fiq_aarch64
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vector_entry serror_aarch64
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apply_at_speculative_wa
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#if RAS_EXTENSION
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msr daifclr, #DAIF_ABT_BIT
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b enter_lower_el_async_ea
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#else
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handle_async_ea
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#endif
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end_vector_entry serror_aarch64
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/* ---------------------------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* ---------------------------------------------------------------------
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*/
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vector_entry sync_exception_aarch32
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/*
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* This exception vector will be the entry point for SMCs and traps
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* that are unhandled at lower ELs most commonly. SP_EL3 should point
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* to a valid cpu context where the general purpose and system register
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* state can be saved.
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*/
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_sync_exception
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end_vector_entry sync_exception_aarch32
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vector_entry irq_aarch32
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_interrupt_exception irq_aarch32
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end_vector_entry irq_aarch32
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vector_entry fiq_aarch32
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apply_at_speculative_wa
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check_and_unmask_ea
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handle_interrupt_exception fiq_aarch32
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end_vector_entry fiq_aarch32
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vector_entry serror_aarch32
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apply_at_speculative_wa
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#if RAS_EXTENSION
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msr daifclr, #DAIF_ABT_BIT
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b enter_lower_el_async_ea
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#else
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handle_async_ea
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#endif
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end_vector_entry serror_aarch32
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#ifdef MONITOR_TRAPS
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.section .rodata.brk_string, "aS"
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brk_location:
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.asciz "Error at instruction 0x"
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brk_message:
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.asciz "Unexpected BRK instruction with value 0x"
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#endif /* MONITOR_TRAPS */
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/* ---------------------------------------------------------------------
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* The following code handles secure monitor calls.
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* Depending upon the execution state from where the SMC has been
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* invoked, it frees some general purpose registers to perform the
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* remaining tasks. They involve finding the runtime service handler
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* that is the target of the SMC & switching to runtime stacks (SP_EL0)
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* before calling the handler.
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*
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* Note that x30 has been explicitly saved and can be used here
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* ---------------------------------------------------------------------
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*/
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func smc_handler
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smc_handler32:
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/* Check whether aarch32 issued an SMC64 */
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tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
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smc_handler64:
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/* NOTE: The code below must preserve x0-x4 */
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/*
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
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* Also set the PSTATE to a known state.
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*/
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bl prepare_el3_entry
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#if ENABLE_PAUTH
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/* Load and program APIAKey firmware key */
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bl pauth_load_bl31_apiakey
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#endif
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/*
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* Populate the parameters for the SMC handler.
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* We already have x0-x4 in place. x5 will point to a cookie (not used
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* now). x6 will point to the context structure (SP_EL3) and x7 will
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* contain flags we need to pass to the handler.
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*/
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mov x5, xzr
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mov x6, sp
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/*
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* Restore the saved C runtime stack value which will become the new
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* SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
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* structure prior to the last ERET from EL3.
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*/
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ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
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/* Switch to SP_EL0 */
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msr spsel, #MODE_SP_EL0
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/*
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* Save the SPSR_EL3 and ELR_EL3 in case there is a world
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* switch during SMC handling.
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* TODO: Revisit if all system registers can be saved later.
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*/
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mrs x16, spsr_el3
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mrs x17, elr_el3
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stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
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|
|
/* Load SCR_EL3 */
|
|
mrs x18, scr_el3
|
|
|
|
/* Clear flag register */
|
|
mov x7, xzr
|
|
|
|
#if ENABLE_RME
|
|
/* Copy SCR_EL3.NSE bit to the flag to indicate caller's security */
|
|
ubfx x7, x18, #SCR_NSE_SHIFT, 1
|
|
|
|
/*
|
|
* Shift copied SCR_EL3.NSE bit by 5 to create space for
|
|
* SCR_EL3.NS bit. Bit 5 of the flag corresponds to
|
|
* the SCR_EL3.NSE bit.
|
|
*/
|
|
lsl x7, x7, #5
|
|
#endif /* ENABLE_RME */
|
|
|
|
/* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
|
|
bfi x7, x18, #0, #1
|
|
|
|
/*
|
|
* Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID
|
|
* passed through x0. Copy the SVE hint bit to flags and mask the
|
|
* bit in smc_fid passed to the standard service dispatcher.
|
|
* A service/dispatcher can retrieve the SVE hint bit state from
|
|
* flags using the appropriate helper.
|
|
*/
|
|
bfi x7, x0, #FUNCID_SVE_HINT_SHIFT, #FUNCID_SVE_HINT_MASK
|
|
bic x0, x0, #(FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT)
|
|
|
|
mov sp, x12
|
|
|
|
/* Get the unique owning entity number */
|
|
ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
|
|
ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
|
|
orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
|
|
|
|
/* Load descriptor index from array of indices */
|
|
adrp x14, rt_svc_descs_indices
|
|
add x14, x14, :lo12:rt_svc_descs_indices
|
|
ldrb w15, [x14, x16]
|
|
|
|
/* Any index greater than 127 is invalid. Check bit 7. */
|
|
tbnz w15, 7, smc_unknown
|
|
|
|
/*
|
|
* Get the descriptor using the index
|
|
* x11 = (base + off), w15 = index
|
|
*
|
|
* handler = (base + off) + (index << log2(size))
|
|
*/
|
|
adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
|
|
lsl w10, w15, #RT_SVC_SIZE_LOG2
|
|
ldr x15, [x11, w10, uxtw]
|
|
|
|
/*
|
|
* Call the Secure Monitor Call handler and then drop directly into
|
|
* el3_exit() which will program any remaining architectural state
|
|
* prior to issuing the ERET to the desired lower EL.
|
|
*/
|
|
#if DEBUG
|
|
cbz x15, rt_svc_fw_critical_error
|
|
#endif
|
|
blr x15
|
|
|
|
b el3_exit
|
|
|
|
smc_unknown:
|
|
/*
|
|
* Unknown SMC call. Populate return value with SMC_UNK and call
|
|
* el3_exit() which will restore the remaining architectural state
|
|
* i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET
|
|
* to the desired lower EL.
|
|
*/
|
|
mov x0, #SMC_UNK
|
|
str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
|
|
b el3_exit
|
|
|
|
smc_prohibited:
|
|
restore_ptw_el1_sys_regs
|
|
ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
|
|
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
|
mov x0, #SMC_UNK
|
|
exception_return
|
|
|
|
#if DEBUG
|
|
rt_svc_fw_critical_error:
|
|
/* Switch to SP_ELx */
|
|
msr spsel, #MODE_SP_ELX
|
|
no_ret report_unhandled_exception
|
|
#endif
|
|
endfunc smc_handler
|
|
|
|
/* ---------------------------------------------------------------------
|
|
* The following code handles exceptions caused by BRK instructions.
|
|
* Following a BRK instruction, the only real valid cause of action is
|
|
* to print some information and panic, as the code that caused it is
|
|
* likely in an inconsistent internal state.
|
|
*
|
|
* This is initially intended to be used in conjunction with
|
|
* __builtin_trap.
|
|
* ---------------------------------------------------------------------
|
|
*/
|
|
#ifdef MONITOR_TRAPS
|
|
func brk_handler
|
|
/* Extract the ISS */
|
|
mrs x10, esr_el3
|
|
ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH
|
|
|
|
/* Ensure the console is initialized */
|
|
bl plat_crash_console_init
|
|
|
|
adr x4, brk_location
|
|
bl asm_print_str
|
|
mrs x4, elr_el3
|
|
bl asm_print_hex
|
|
bl asm_print_newline
|
|
|
|
adr x4, brk_message
|
|
bl asm_print_str
|
|
mov x4, x10
|
|
mov x5, #28
|
|
bl asm_print_hex_bits
|
|
bl asm_print_newline
|
|
|
|
no_ret plat_panic_handler
|
|
endfunc brk_handler
|
|
#endif /* MONITOR_TRAPS */
|