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arm-trusted-firmware/plat/intel/soc
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Sieu Mun Tang e60bedd5e1 feat(intel): clock manager PLL configuration for Agilex5 platform 
Read the hand-off data and configure the clock manager main
and peripheral PLL and few other misc updates.

Change-Id: I3c5cbaf7a677a022ef24b0e679860e6ee195f16a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
2024-10-25 09:29:20 +08:00
..
agilex Merge "fix(intel): correct macro naming" into integration 2024-10-24 16:59:57 +02:00
agilex5 feat(intel): clock manager PLL configuration for Agilex5 platform 2024-10-25 09:29:20 +08:00
common fix(intel): update all the platforms hand-off data offset value 2024-10-24 12:52:18 +08:00
n5x Merge "fix(intel): correct macro naming" into integration 2024-10-24 16:59:57 +02:00
stratix10 Merge "fix(intel): correct macro naming" into integration 2024-10-24 16:59:57 +02:00