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https://github.com/ARM-software/arm-trusted-firmware.git
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e5d5951973
Changed the names for consistency with the rest of the library. Introduced new helpers that manipulate the active translation tables context. Change-Id: Icaca56b67fcf6a96e88aa3c7e47411162e8e6856 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
148 lines
3.9 KiB
C
148 lines
3.9 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <debug.h>
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#include <platform_def.h>
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#include <xlat_tables_defs.h>
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#include <xlat_tables_v2.h>
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#include "xlat_tables_private.h"
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/*
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* MMU configuration register values for the active translation context. Used
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* from the MMU assembly helpers.
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*/
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uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
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/*
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* Each platform can define the size of its physical and virtual address spaces.
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* If the platform hasn't defined one or both of them, default to
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* ADDR_SPACE_SIZE. The latter is deprecated, though.
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*/
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#if ERROR_DEPRECATED
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# ifdef ADDR_SPACE_SIZE
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# error "ADDR_SPACE_SIZE is deprecated. Use PLAT_xxx_ADDR_SPACE_SIZE instead."
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# endif
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#elif defined(ADDR_SPACE_SIZE)
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# ifndef PLAT_PHY_ADDR_SPACE_SIZE
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# define PLAT_PHY_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
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# endif
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# ifndef PLAT_VIRT_ADDR_SPACE_SIZE
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# define PLAT_VIRT_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
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# endif
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#endif
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/*
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* Allocate and initialise the default translation context for the BL image
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* currently executing.
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*/
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REGISTER_XLAT_CONTEXT(tf, MAX_MMAP_REGIONS, MAX_XLAT_TABLES,
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PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE);
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void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, size_t size,
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unsigned int attr)
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{
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mmap_region_t mm = MAP_REGION(base_pa, base_va, size, attr);
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mmap_add_region_ctx(&tf_xlat_ctx, &mm);
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}
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void mmap_add(const mmap_region_t *mm)
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{
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mmap_add_ctx(&tf_xlat_ctx, mm);
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}
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#if PLAT_XLAT_TABLES_DYNAMIC
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int mmap_add_dynamic_region(unsigned long long base_pa, uintptr_t base_va,
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size_t size, unsigned int attr)
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{
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mmap_region_t mm = MAP_REGION(base_pa, base_va, size, attr);
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return mmap_add_dynamic_region_ctx(&tf_xlat_ctx, &mm);
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}
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int mmap_remove_dynamic_region(uintptr_t base_va, size_t size)
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{
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return mmap_remove_dynamic_region_ctx(&tf_xlat_ctx,
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base_va, size);
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}
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#endif /* PLAT_XLAT_TABLES_DYNAMIC */
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void init_xlat_tables(void)
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{
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assert(tf_xlat_ctx.xlat_regime == EL_REGIME_INVALID);
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unsigned int current_el = xlat_arch_current_el();
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if (current_el == 1U) {
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tf_xlat_ctx.xlat_regime = EL1_EL0_REGIME;
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} else {
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assert(current_el == 3U);
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tf_xlat_ctx.xlat_regime = EL3_REGIME;
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}
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init_xlat_tables_ctx(&tf_xlat_ctx);
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}
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int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr)
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{
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return xlat_get_mem_attributes_ctx(&tf_xlat_ctx, base_va, attr);
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}
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int xlat_change_mem_attributes(uintptr_t base_va, size_t size, uint32_t attr)
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{
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return xlat_change_mem_attributes_ctx(&tf_xlat_ctx, base_va, size, attr);
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}
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/*
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* If dynamic allocation of new regions is disabled then by the time we call the
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* function enabling the MMU, we'll have registered all the memory regions to
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* map for the system's lifetime. Therefore, at this point we know the maximum
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* physical address that will ever be mapped.
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*
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* If dynamic allocation is enabled then we can't make any such assumption
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* because the maximum physical address could get pushed while adding a new
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* region. Therefore, in this case we have to assume that the whole address
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* space size might be mapped.
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*/
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#ifdef PLAT_XLAT_TABLES_DYNAMIC
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#define MAX_PHYS_ADDR tf_xlat_ctx.pa_max_address
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#else
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#define MAX_PHYS_ADDR tf_xlat_ctx.max_pa
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#endif
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#ifdef AARCH32
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void enable_mmu_secure(unsigned int flags)
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{
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setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
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tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
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tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
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enable_mmu_direct(flags);
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}
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#else
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void enable_mmu_el1(unsigned int flags)
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{
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setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
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tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
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tf_xlat_ctx.va_max_address, EL1_EL0_REGIME);
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enable_mmu_direct_el1(flags);
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}
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void enable_mmu_el3(unsigned int flags)
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{
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setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
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tf_xlat_ctx.base_table, MAX_PHYS_ADDR,
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tf_xlat_ctx.va_max_address, EL3_REGIME);
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enable_mmu_direct_el3(flags);
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}
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#endif /* AARCH32 */
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