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https://github.com/ARM-software/arm-trusted-firmware.git
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af994ae8a0
Since CPUs such as cortex-a76 are hardware-assisted coherent, coherent memory section is not required for them and should be an optional section. Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> Change-Id: I03c8e9148ca1780b8af92024359698f4452f7129
95 lines
2.4 KiB
C
95 lines
2.4 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include "qemu_private.h"
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#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
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bl1_tzram_layout.total_base, \
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bl1_tzram_layout.total_size, \
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MT_MEMORY | MT_RW | EL3_PAS)
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#define MAP_BL1_RO MAP_REGION_FLAT( \
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BL_CODE_BASE, \
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BL1_CODE_END - BL_CODE_BASE, \
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MT_CODE | EL3_PAS), \
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MAP_REGION_FLAT( \
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BL1_RO_DATA_BASE, \
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BL1_RO_DATA_END \
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- BL_RO_DATA_BASE, \
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MT_RO_DATA | EL3_PAS)
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#if USE_COHERENT_MEM
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#define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
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BL_COHERENT_RAM_BASE, \
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BL_COHERENT_RAM_END \
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- BL_COHERENT_RAM_BASE, \
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MT_DEVICE | MT_RW | EL3_PAS)
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#endif
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/* Data structure which holds the extents of the trusted SRAM for BL1*/
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static meminfo_t bl1_tzram_layout;
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meminfo_t *bl1_plat_sec_mem_layout(void)
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{
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return &bl1_tzram_layout;
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}
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void bl1_early_platform_setup(void)
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{
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/* Initialize the console to provide early debug support */
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qemu_console_init();
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = BL_RAM_BASE;
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bl1_tzram_layout.total_size = BL_RAM_SIZE;
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}
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/******************************************************************************
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* Perform the very early platform specific architecture setup. This only
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* does basic initialization. Later architectural setup (bl1_arch_setup())
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* does not do anything platform specific.
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*****************************************************************************/
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#ifdef __aarch64__
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#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__)
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#else
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#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
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#endif
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void bl1_plat_arch_setup(void)
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{
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const mmap_region_t bl_regions[] = {
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MAP_BL1_TOTAL,
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MAP_BL1_RO,
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#if USE_COHERENT_MEM
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MAP_BL_COHERENT_RAM,
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#endif
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{0}
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};
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setup_page_tables(bl_regions, plat_qemu_get_mmap());
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#ifdef __aarch64__
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enable_mmu_el3(0);
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#else
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enable_mmu_svc_mon(0);
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#endif
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}
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void bl1_platform_setup(void)
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{
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plat_qemu_io_setup();
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}
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