Ghennadi Procopciuc e4462dae81 feat(nxp-clk): enable UART clock ... Before this change, the internal oscillator clocked the UART with a frequency of 48MHz. With the necessary support added, the UART clock rate is increased to 125MHz by changing the clock source from FIRC to PERIPH PLL PHI3. Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>		2024-08-20 16:28:56 +03:00
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common	build: unify verbosity handling	2024-06-14 15:54:48 +00:00
s32/s32g274ardb2	feat(nxp-clk): enable UART clock	2024-08-20 16:28:56 +03:00
soc-ls1028a	fix(layerscape): fix errata a008850	2022-11-22 14:56:19 +08:00
soc-ls1043a	fix(layerscape): unlock write access SMMU_CBn_ACTLR	2022-12-06 22:46:10 +08:00
soc-ls1046a	refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3	2023-03-15 11:43:14 +00:00
soc-ls1088a	fix(tree): correct some typos	2023-05-09 15:57:12 +01:00
soc-lx2160a	build: consolidate directory creation rules	2024-07-22 09:41:30 +00:00