Bipin Ravi c1aa3fa555 fix(cpus): workaround for Cortex X3 erratum 2641945 ... Cortex X3 erratum 2641945 is a Cat B erratum that applies to all revisions <= r1p0 and is fixed in r1p1. The workaround is to disable the affected L1 data cache prefetcher by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance penalty of ~1%. Contact Arm for an alternate workaround that impacts power. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>		2024-01-25 17:14:54 -06:00
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arm_arch_svc	fix(services): disable workaround discovery on aarch32 for now	2023-08-04 16:02:28 +02:00
spd	feat(optee): enable transfer list in opteed	2024-01-17 12:18:09 -08:00
std_svc	fix(cpus): workaround for Cortex X3 erratum 2641945	2024-01-25 17:14:54 -06:00