mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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e3ec6ff4b2
rk3588 is an Octa-core soc with Cortex-a55/a76 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com> Change-Id: I598109f15a2efd5b33aedd176cf708c08cb1dcf4
221 lines
7 KiB
C
221 lines
7 KiB
C
/*
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* Copyright (c) 2024, Rockchip, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLAT_DEF_H__
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#define __PLAT_DEF_H__
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#define SIZE_K(n) ((n) * 1024)
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#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits))
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define UMCTL0_BASE 0xf7000000
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#define UMCTL1_BASE 0xf8000000
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#define UMCTL2_BASE 0xf9000000
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#define UMCTL3_BASE 0xfa000000
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#define GIC600_BASE 0xfe600000
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#define GIC600_SIZE SIZE_K(64)
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#define DAPLITE_BASE 0xfd100000
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#define PMU0SGRF_BASE 0xfd580000
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#define PMU1SGRF_BASE 0xfd582000
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#define BUSSGRF_BASE 0xfd586000
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#define DSUSGRF_BASE 0xfd587000
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#define PMU0GRF_BASE 0xfd588000
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#define PMU1GRF_BASE 0xfd58a000
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#define SYSGRF_BASE 0xfd58c000
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#define BIGCORE0GRF_BASE 0xfd590000
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#define BIGCORE1GRF_BASE 0xfd592000
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#define LITCOREGRF_BASE 0xfd594000
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#define DSUGRF_BASE 0xfd598000
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#define DDR01GRF_BASE 0xfd59c000
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#define DDR23GRF_BASE 0xfd59d000
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#define CENTERGRF_BASE 0xfd59e000
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#define GPUGRF_BASE 0xfd5a0000
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#define NPUGRF_BASE 0xfd5a2000
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#define USBGRF_BASE 0xfd5ac000
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#define PHPGRF_BASE 0xfd5b0000
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#define PCIE3PHYGRF_BASE 0xfd5b8000
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#define USB2PHY0_GRF_BASE 0xfd5d0000
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#define USB2PHY1_GRF_BASE 0xfd5d4000
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#define USB2PHY2_GRF_BASE 0xfd5d8000
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#define USB2PHY3_GRF_BASE 0xfd5dc000
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#define PMU0IOC_BASE 0xfd5f0000
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#define PMU1IOC_BASE 0xfd5f4000
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#define BUSIOC_BASE 0xfd5f8000
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#define VCCIO1_4_IOC_BASE 0xfd5f9000
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#define VCCIO3_5_IOC_BASE 0xfd5fa000
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#define VCCIO2_IOC_BASE 0xfd5fb000
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#define VCCIO6_IOC_BASE 0xfd5fc000
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#define SRAM_BASE 0xff000000
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#define PMUSRAM_BASE 0xff100000
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#define PMUSRAM_SIZE SIZE_K(128)
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#define PMUSRAM_RSIZE SIZE_K(64)
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#define CRU_BASE 0xfd7c0000
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#define PHP_CRU_BASE 0xfd7c8000
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#define SCRU_BASE 0xfd7d0000
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#define BUSSCRU_BASE 0xfd7d8000
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#define PMU1SCRU_BASE 0xfd7e0000
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#define PMU1CRU_BASE 0xfd7f0000
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#define DDR0CRU_BASE 0xfd800000
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#define DDR1CRU_BASE 0xfd804000
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#define DDR2CRU_BASE 0xfd808000
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#define DDR3CRU_BASE 0xfd80c000
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#define BIGCORE0CRU_BASE 0xfd810000
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#define BIGCORE1CRU_BASE 0xfd812000
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#define LITCRU_BASE 0xfd814000
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#define DSUCRU_BASE 0xfd818000
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#define I2C0_BASE 0xfd880000
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#define UART0_BASE 0xfd890000
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#define GPIO0_BASE 0xfd8a0000
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#define PWM0_BASE 0xfd8b0000
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#define PMUPVTM_BASE 0xfd8c0000
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#define TIMER_HP_BASE 0xfd8c8000
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#define PMU0_BASE 0xfd8d0000
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#define PMU1_BASE 0xfd8d4000
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#define PMU2_BASE 0xfd8d8000
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#define PMU_BASE PMU0_BASE
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#define PMUWDT_BASE 0xfd8e0000
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#define PMUTIMER_BASE 0xfd8f0000
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#define OSC_CHK_BASE 0xfd9b0000
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#define VOP_BASE 0xfdd90000
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#define HDMIRX_BASE 0xfdee0000
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#define MSCH0_BASE 0xfe000000
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#define MSCH1_BASE 0xfe002000
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#define MSCH2_BASE 0xfe004000
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#define MSCH3_BASE 0xfe006000
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#define FIREWALL_DSU_BASE 0xfe010000
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#define FIREWALL_DDR_BASE 0xfe030000
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#define FIREWALL_SYSMEM_BASE 0xfe038000
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#define DDRPHY0_BASE 0xfe0c0000
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#define DDRPHY1_BASE 0xfe0d0000
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#define DDRPHY2_BASE 0xfe0e0000
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#define DDRPHY3_BASE 0xfe0f0000
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#define TIMER_DDR_BASE 0xfe118000
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#define KEYLADDER_BASE 0xfe380000
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#define CRYPTO_S_BASE 0xfe390000
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#define OTP_S_BASE 0xfe3a0000
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#define DCF_BASE 0xfe3c0000
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#define STIMER0_BASE 0xfe3d0000
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#define WDT_S_BASE 0xfe3e0000
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#define CRYPTO_S_BY_KEYLAD_BASE 0xfe420000
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#define NSTIMER0_BASE 0xfeae0000
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#define NSTIMER1_BASE 0xfeae8000
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#define WDT_NS_BASE 0xfeaf0000
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#define UART1_BASE 0xfeb40000
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#define UART2_BASE 0xfeb50000
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#define UART3_BASE 0xfeb60000
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#define UART4_BASE 0xfeb70000
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#define UART5_BASE 0xfeb80000
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#define UART6_BASE 0xfeb90000
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#define UART7_BASE 0xfeba0000
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#define UART8_BASE 0xfebb0000
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#define UART9_BASE 0xfebc0000
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#define GPIO1_BASE 0xfec20000
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#define GPIO2_BASE 0xfec30000
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#define GPIO3_BASE 0xfec40000
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#define GPIO4_BASE 0xfec50000
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#define MAILBOX1_BASE 0xfec70000
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#define OTP_NS_BASE 0xfecc0000
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#define INTMUX0_DDR_BASE 0Xfecf8000
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#define INTMUX1_DDR_BASE 0Xfecfc000
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#define STIMER1_BASE 0xfed30000
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/**************************************************************************
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* sys sram allocation
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**************************************************************************/
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#define SRAM_ENTRY_BASE SRAM_BASE
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#define SRAM_PMUM0_SHMEM_BASE (SRAM_ENTRY_BASE + SIZE_K(3))
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#define SRAM_LD_BASE (SRAM_ENTRY_BASE + SIZE_K(4))
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#define SRAM_LD_SIZE SIZE_K(64)
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#define SRAM_LD_SP (SRAM_LD_BASE + SRAM_LD_SIZE -\
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128)
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/**************************************************************************
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* share mem region allocation: 1M~2M
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**************************************************************************/
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#define DDR_SHARE_MEM SIZE_K(1024)
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#define DDR_SHARE_SIZE SIZE_K(64)
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#define SHARE_MEM_BASE DDR_SHARE_MEM
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#define SHARE_MEM_PAGE_NUM 15
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#define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4)
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#define SCMI_SHARE_MEM_BASE (SHARE_MEM_BASE + SHARE_MEM_SIZE)
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#define SCMI_SHARE_MEM_SIZE SIZE_K(4)
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/**************************************************************************
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* UART related constants
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**************************************************************************/
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#define RK_DBG_UART_BASE UART2_BASE
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#define RK_DBG_UART_BAUDRATE 1500000
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#define RK_DBG_UART_CLOCK 24000000
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/******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 24000000
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#define SYS_COUNTER_FREQ_IN_MHZ 24
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/******************************************************************************
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* GIC-600 & interrupt handling related constants
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******************************************************************************/
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/* Base rk_platform compatible GIC memory map */
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#define PLAT_GICD_BASE GIC600_BASE
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#define PLAT_GICC_BASE 0
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#define PLAT_GICR_BASE (GIC600_BASE + 0x80000)
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#define PLAT_GICITS0_BASE 0xfe640000
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#define PLAT_GICITS1_BASE 0xfe660000
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/******************************************************************************
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* sgi, ppi
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******************************************************************************/
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#define RK_IRQ_SEC_SGI_0 8
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#define RK_IRQ_SEC_SGI_1 9
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#define RK_IRQ_SEC_SGI_2 10
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#define RK_IRQ_SEC_SGI_3 11
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#define RK_IRQ_SEC_SGI_4 12
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#define RK_IRQ_SEC_SGI_5 13
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#define RK_IRQ_SEC_SGI_6 14
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#define RK_IRQ_SEC_SGI_7 15
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#define RK_IRQ_SEC_PHY_TIMER 29
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_RK_GICV3_G1S_IRQS \
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INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
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INTR_GROUP1S, GIC_INTR_CFG_LEVEL)
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#define PLAT_RK_GICV3_G0_IRQS \
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INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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/******************************************************************************
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* pm reg region memory
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******************************************************************************/
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#define ROCKCHIP_PM_REG_REGION_MEM_SIZE SIZE_K(4)
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#endif /* __PLAT_DEF_H__ */
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