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https://github.com/ARM-software/arm-trusted-firmware.git
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e3ec6ff4b2
rk3588 is an Octa-core soc with Cortex-a55/a76 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com> Change-Id: I598109f15a2efd5b33aedd176cf708c08cb1dcf4
119 lines
3.9 KiB
C
119 lines
3.9 KiB
C
/*
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* Copyright (c) 2024, Rockchip, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include <plat/common/common_def.h>
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#include <rk3588_def.h>
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#define DEBUG_XLAT_TABLE 0
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#if DEBUG_XLAT_TABLE
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#define PLATFORM_STACK_SIZE 0x800
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#elif IMAGE_BL1
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#define PLATFORM_STACK_SIZE 0x440
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#elif IMAGE_BL2
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#define PLATFORM_STACK_SIZE 0x400
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#elif IMAGE_BL31
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#define PLATFORM_STACK_SIZE 0x800
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#elif IMAGE_BL32
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#define PLATFORM_STACK_SIZE 0x440
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#endif
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define PLATFORM_SYSTEM_COUNT 1
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#define PLATFORM_CLUSTER_COUNT 1
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#define PLATFORM_CLUSTER0_CORE_COUNT 8
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#define PLATFORM_CLUSTER1_CORE_COUNT 0
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_RK_CLST_TO_CPUID_SHIFT 8
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE 1
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE 2
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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/* TF txet, ro, rw, Size: 512KB */
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#define TZRAM_BASE (0x0)
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#define TZRAM_SIZE (0x100000)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL3-1 at the top of the Trusted RAM
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*/
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#define BL31_BASE (TZRAM_BASE + 0x40000)
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES 18
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#define MAX_MMAP_REGIONS 27
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/*
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* Define GICD and GICC and GICR base
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*/
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#define PLAT_RK_GICD_BASE PLAT_GICD_BASE
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#define PLAT_RK_GICC_BASE PLAT_GICC_BASE
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#define PLAT_RK_GICR_BASE PLAT_GICR_BASE
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#define PLAT_RK_UART_BASE RK_DBG_UART_BASE
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#define PLAT_RK_UART_CLOCK RK_DBG_UART_CLOCK
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#define PLAT_RK_UART_BAUDRATE RK_DBG_UART_BAUDRATE
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#define PLAT_RK_PRIMARY_CPU 0x0
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#endif /* __PLATFORM_DEF_H__ */
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