mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 18:14:24 +00:00
e3ec6ff4b2
rk3588 is an Octa-core soc with Cortex-a55/a76 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com> Change-Id: I598109f15a2efd5b33aedd176cf708c08cb1dcf4
198 lines
4.9 KiB
C
198 lines
4.9 KiB
C
/*
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* Copyright (c) 2024, Rockchip, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SOC_H__
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#define __SOC_H__
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enum pll_id {
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APLL_ID,
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DPLL_ID,
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GPLL_ID,
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CPLL_ID,
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NPLL_ID,
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VPLL_ID,
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};
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enum pmu_pll_id {
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PPLL_ID = 0,
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HPLL_ID
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};
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enum cru_mode_con00 {
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CLK_APLL,
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CLK_DPLL,
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CLK_CPLL,
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CLK_GPLL,
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CLK_REVSERVED,
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CLK_NPLL,
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CLK_VPLL,
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CLK_USBPLL,
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};
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#define KHz 1000
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#define MHz (1000 * KHz)
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#define OSC_HZ (24 * MHz)
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/* CRU */
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#define GLB_SRST_FST_CFG_VAL 0xfdb9
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#define CRU_PLLS_CON(pll_id, i) (0x160 + (pll_id) * 0x20 + (i) * 0x4)
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#define CRU_PLL_CON(i) ((i) * 0x4)
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#define CRU_MODE_CON0 0x280
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#define CRU_CLKSEL_CON(i) ((i) * 0x4 + 0x300)
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#define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
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#define CRU_CLKGATE_CON_CNT 78
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#define CRU_SOFTRST_CON(i) ((i) * 0x4 + 0xa00)
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#define CRU_GLB_CNT_TH 0xc00
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#define CRU_GLB_SRST_FST 0xc08
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#define CRU_GLB_SRST_SND 0xc0c
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#define CRU_GLB_RST_CON 0xc10
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#define CRU_GLB_RST_ST 0xc04
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#define CRU_SDIO_CON0 0xc24
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#define CRU_SDIO_CON1 0xc28
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#define CRU_SDMMC_CON0 0xc30
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#define CRU_SDMMC_CON1 0xc34
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#define CRU_AUTOCS_CON0(id) (0xd00 + (id) * 8)
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#define CRU_AUTOCS_CON1(id) (0xd04 + (id) * 8)
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#define CRU_AUTOCS_ID_CNT 74
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#define CRU_PLLCON0_M_MASK 0x3ff
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#define CRU_PLLCON0_M_SHIFT 0
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#define CRU_PLLCON1_P_MASK 0x3f
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#define CRU_PLLCON1_P_SHIFT 0
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#define CRU_PLLCON1_S_MASK 0x7
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#define CRU_PLLCON1_S_SHIFT 6
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#define CRU_PLLCON2_K_MASK 0xffff
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#define CRU_PLLCON2_K_SHIFT 0
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#define CRU_PLLCON1_PWRDOWN BIT(13)
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#define CRU_PLLCON6_LOCK_STATUS BIT(15)
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#define CRU_BIGCPU02_RST_MSK 0x30
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#define CRU_BIGCPU13_RST_MSK 0x300
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#define PHPCRU_CLKGATE_CON 0x800
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#define PHPCRU_CLKGATE_CON_CNT 1
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#define SECURECRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800)
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#define SECURECRU_CLKGATE_CON_CNT 4
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#define PMU1CRU_CLKGATE_CON_CNT 6
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/* CENTER GRF */
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#define CENTER_GRF_CON(i) ((i) * 4)
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/* PMU1GRF */
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#define PMU1GRF_SOC_CON(n) ((n) * 4)
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#define PMU1GRF_SOC_ST 0x60
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#define PMU1GRF_OS_REG(n) (0x200 + ((n) * 4))
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#define PMU_MCU_HALT BIT(7)
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#define PMU_MCU_SLEEP BIT(9)
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#define PMU_MCU_DEEPSLEEP BIT(10)
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#define PMU_MCU_STOP_MSK \
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(PMU_MCU_HALT | PMU_MCU_SLEEP | PMU_MCU_DEEPSLEEP)
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/* SYSGRF */
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#define SYS_GRF_NOC_CON(n) (0x100 + (n) * 4)
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#define SYS_GRF_SOC_CON(n) (0x300 + (n) * 4)
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#define SYS_GRF_SOC_STATUS(n) (0x380 + (n) * 4)
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#define SYS_GRF_LITTLE_CPUS_WFE 0xf
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#define SYS_GRF_CORE0_CPUS_WFE 0x30
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#define SYS_GRF_CORE1_CPUS_WFE 0xc0
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#define SYS_GRF_BIG_CPUS_WFE 0xf0
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#define SYS_GRF_LITTLE_CPUS_WFI 0xf00
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#define SYS_GRF_CORE0_CPUS_WFI 0x3000
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#define SYS_GRF_CORE1_CPUS_WFI 0xc000
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/* pvtm */
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#define PVTM_CON(i) (0x4 + (i) * 4)
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#define PVTM_INTEN 0x70
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#define PVTM_INTSTS 0x74
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#define PVTM_STATUS(i) (0x80 + (i) * 4)
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#define PVTM_CALC_CNT 0x200
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enum pvtm_con0 {
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pvtm_start = 0,
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pvtm_osc_en = 1,
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pvtm_osc_sel = 2,
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pvtm_rnd_seed_en = 5,
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};
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/* timer */
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#define TIMER_LOAD_COUNT0 0x00
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#define TIMER_LOAD_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0c
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_INTSTATUS 0x18
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#define TIMER_DIS 0x0
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#define TIMER_EN 0x1
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#define TIMER_FMODE (0x0 << 1)
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#define TIMER_RMODE (0x1 << 1)
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#define STIMER0_CHN_BASE(n) (STIMER0_BASE + 0x20 * (n))
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#define STIMER1_CHN_BASE(n) (STIMER1_BASE + 0x20 * (n))
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/* cpu timer */
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#define TIMER_HP_REVISION 0x0
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#define TIMER_HP_CTRL 0x4
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#define TIMER_HP_INT_EN 0x8
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#define TIMER_HP_T24_GCD 0xc
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#define TIMER_HP_T32_GCD 0x10
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#define TIMER_HP_LOAD_COUNT0 0x14
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#define TIMER_HP_LOAD_COUNT1 0x18
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#define TIMER_HP_T24_DELAT_COUNT0 0x1c
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#define TIMER_HP_T24_DELAT_COUNT1 0x20
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#define TIMER_HP_CURR_32K_VALUE0 0x24
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#define TIMER_HP_CURR_32K_VALUE1 0x28
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#define TIMER_HP_CURR_TIMER_VALUE0 0x2c
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#define TIMER_HP_CURR_TIMER_VALUE1 0x30
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#define TIMER_HP_T24_32BEGIN0 0x34
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#define TIMER_HP_T24_32BEGIN1 0x38
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#define TIMER_HP_T32_24END0 0x3c
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#define TIMER_HP_T32_24END1 0x40
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#define TIMER_HP_BEGIN_END_VALID 0x44
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#define TIMER_HP_SYNC_REQ 0x48
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#define TIMER_HP_INTR_STATUS 0x4c
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/* GPIO */
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#define GPIO_SWPORT_DR_L 0x0000
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#define GPIO_SWPORT_DR_H 0x0004
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#define GPIO_SWPORT_DDR_L 0x0008
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#define GPIO_SWPORT_DDR_H 0x000c
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#define GPIO_INT_EN_L 0x0010
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#define GPIO_INT_EN_H 0x0014
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#define GPIO_INT_MASK_L 0x0018
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#define GPIO_INT_MASK_H 0x001c
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#define GPIO_INT_TYPE_L 0x0020
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#define GPIO_INT_TYPE_H 0x0024
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#define GPIO_INT_POLARITY_L 0x0028
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#define GPIO_INT_POLARITY_H 0x002c
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#define GPIO_INT_BOTHEDGE_L 0x0030
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#define GPIO_INT_BOTHEDGE_H 0x0034
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#define GPIO_DEBOUNCE_L 0x0038
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#define GPIO_DEBOUNCE_H 0x003c
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#define GPIO_DBCLK_DIV_EN_L 0x0040
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#define GPIO_DBCLK_DIV_EN_H 0x0044
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#define GPIO_DBCLK_DIV_CON 0x0048
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#define GPIO_INT_STATUS 0x0050
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#define GPIO_INT_RAWSTATUS 0x0058
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#define GPIO_PORT_EOI_L 0x0060
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#define GPIO_PORT_EOI_H 0x0064
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#define GPIO_EXT_PORT 0x0070
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#define GPIO_VER_ID 0x0078
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/* DDRGRF */
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#define DDRGRF_CHA_CON(i) ((i) * 4)
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#define DDRGRF_CHB_CON(i) (0x30 + (i) * 4)
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#define DDR_CHN_CNT 4
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#endif /* __SOC_H__ */
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