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https://github.com/ARM-software/arm-trusted-firmware.git
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e3ec6ff4b2
rk3588 is an Octa-core soc with Cortex-a55/a76 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com> Change-Id: I598109f15a2efd5b33aedd176cf708c08cb1dcf4
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/*
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* Copyright (c) 2024, Rockchip, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SECURE_H
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#define SECURE_H
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/* DSUSGRF */
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#define DSU_SGRF_SOC_CON(i) ((i) * 4)
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#define DSUSGRF_SOC_CON(i) ((i) * 4)
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#define DSUSGRF_SOC_CON_CNT 13
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#define DSUSGRF_DDR_HASH_CON(i) (0x240 + (i) * 4)
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#define DSUSGRF_DDR_HASH_CON_CNT 8
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/* PMUSGRF */
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#define PMU1SGRF_SOC_CON(n) ((n) * 4)
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/* SGRF */
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#define SGRF_SOC_CON(i) ((i) * 4)
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#define SGRF_FIREWALL_CON(i) (0x240 + (i) * 4)
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#define SGRF_FIREWALL_CON_CNT 32
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/* ddr firewall */
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#define FIREWALL_DDR_RGN(i) ((i) * 0x4)
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#define FIREWALL_DDR_RGN_CNT 16
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#define FIREWALL_DDR_MST(i) (0x40 + (i) * 0x4)
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#define FIREWALL_DDR_MST_CNT 42
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#define FIREWALL_DDR_CON 0xf0
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#define FIREWALL_SYSMEM_RGN(i) ((i) * 0x4)
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#define FIREWALL_SYSMEM_RGN_CNT 8
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#define FIREWALL_SYSMEM_MST(i) (0x40 + (i) * 0x4)
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#define FIREWALL_SYSMEM_MST_CNT 43
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#define FIREWALL_SYSMEM_CON 0xf0
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#define FIREWALL_DSU_RGN(i) ((i) * 0x4)
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#define FIREWALL_DSU_RGN_CNT 16
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#define FIREWALL_DSU_MST(i) (0x40 + (i) * 0x4)
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#define FIREWALL_DSU_MST_CNT 2
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#define FIREWALL_DSU_CON(i) (0xf0 + (i) * 4)
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#define FIREWALL_DSU_CON_CNT 4
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#define PLAT_MAX_DDR_CAPACITY_MB 0x8000 /* for 32Gb */
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#define RG_MAP_SECURE(top, base) \
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(((((top) - 1) & 0x7fff) << 16) | ((base) & 0x7fff))
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#define RG_MAP_SRAM_SECURE(top_kb, base_kb) \
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(((((top_kb) / 4 - 1) & 0xff) << 16) | ((base_kb) / 4 & 0xff))
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void secure_timer_init(void);
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void sgrf_init(void);
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#endif /* SECURE_H */
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