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https://github.com/ARM-software/arm-trusted-firmware.git
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3cedc47b1d
Since TC3 and TC4 share most components in the hardware design, they can reuse the device tree binding. For this reason, this patch extracts the common modules from tc3.dts and put into the file tc3-4-based.dtsi. As a result, a new created tc4.dts file includes tc3-4-based.dtsi for support DT binding for the TC4 platform. Change-Id: Ib7497162cb131d94a722aeaa14a1a37fb0095829 Signed-off-by: Leo Yan <leo.yan@arm.com>
84 lines
1.7 KiB
Text
84 lines
1.7 KiB
Text
/*
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* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define LIT_CAPACITY 239
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#define MID_CAPACITY 686
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#define BIG_CAPACITY 1024
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#define MHU_TX_COMPAT "arm,mhuv3"
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#define MHU_TX_INT_NAME ""
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#define MHU_RX_COMPAT "arm,mhuv3"
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#define MHU_OFFSET 0x10000
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#define MHU_MBOX_CELLS 3
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#define MHU_RX_INT_NUM 300
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#define MHU_RX_INT_NAME "combined-mbx"
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#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
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#define UARTCLK_FREQ 3750000
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#if TARGET_FLAVOUR_FVP
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#define DPU_ADDR 4000000000
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#define DPU_IRQ 579
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#elif TARGET_FLAVOUR_FPGA
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#define DPU_ADDR 2cc00000
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#define DPU_IRQ 69
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#endif
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#include "tc-base.dtsi"
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/ {
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cpus {
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CPU2:cpu@200 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU3:cpu@300 {
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clocks = <&scmi_dvfs 1>;
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capacity-dmips-mhz = <MID_CAPACITY>;
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};
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CPU6:cpu@600 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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CPU7:cpu@700 {
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clocks = <&scmi_dvfs 2>;
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capacity-dmips-mhz = <BIG_CAPACITY>;
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};
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};
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gic: interrupt-controller@GIC_CTRL_ADDR {
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ppi-partitions {
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ppi_partition_little: interrupt-partition-0 {
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affinity = <&CPU0>, <&CPU1>;
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};
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ppi_partition_mid: interrupt-partition-1 {
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affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
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};
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ppi_partition_big: interrupt-partition-2 {
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affinity = <&CPU6>, <&CPU7>;
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};
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};
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};
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sram: sram@6000000 {
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cpu_scp_scmi_p2a: scp-shmem@80 {
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compatible = "arm,scmi-shmem";
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reg = <0x80 0x80>;
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};
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};
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firmware {
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scmi {
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mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
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shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
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};
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};
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};
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