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e37dfd3c57
Errata report order is enforced to be in ascending order. To achieve this with the errata framework this has to be done at the definition level. Also rename the disable_non_temporal_hint to its erratum number to conform to convention. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Id474872afebf361ab3d21c454ab3624db8354045
409 lines
11 KiB
ArmAsm
409 lines
11 KiB
ArmAsm
/*
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* Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <cortex_a53.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include <lib/cpus/errata.h>
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#if A53_DISABLE_NON_TEMPORAL_HINT
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#undef ERRATA_A53_836870
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#define ERRATA_A53_836870 1
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#endif
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func cortex_a53_disable_dcache
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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ret
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endfunc cortex_a53_disable_dcache
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a53_disable_smp
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mrs x0, CORTEX_A53_ECTLR_EL1
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bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
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msr CORTEX_A53_ECTLR_EL1, x0
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isb
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dsb sy
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ret
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endfunc cortex_a53_disable_smp
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #819472.
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* This applies only to revision <= r0p1 of Cortex A53.
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* Due to the nature of the errata it is applied unconditionally
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* when built in, report it as applicable in this case
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* ---------------------------------------------------
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*/
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func check_errata_819472
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#if ERRATA_A53_819472
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mov x0, #ERRATA_APPLIES
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ret
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#else
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mov x1, #0x01
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b cpu_rev_var_ls
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#endif
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endfunc check_errata_819472
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #824069.
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* This applies only to revision <= r0p2 of Cortex A53.
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* Due to the nature of the errata it is applied unconditionally
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* when built in, report it as applicable in this case
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* ---------------------------------------------------
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*/
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func check_errata_824069
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#if ERRATA_A53_824069
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mov x0, #ERRATA_APPLIES
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ret
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#else
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mov x1, #0x02
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b cpu_rev_var_ls
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#endif
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endfunc check_errata_824069
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #826319.
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* This applies only to revision <= r0p2 of Cortex A53.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a53_826319_wa
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/*
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* Compare x0 against revision r0p2
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*/
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mov x17, x30
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bl check_errata_826319
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cbz x0, 1f
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mrs x1, CORTEX_A53_L2ACTLR_EL1
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bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
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orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
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msr CORTEX_A53_L2ACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a53_826319_wa
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func check_errata_826319
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mov x1, #0x02
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b cpu_rev_var_ls
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endfunc check_errata_826319
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #827319.
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* This applies only to revision <= r0p2 of Cortex A53.
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* Due to the nature of the errata it is applied unconditionally
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* when built in, report it as applicable in this case
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* ---------------------------------------------------
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*/
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func check_errata_827319
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#if ERRATA_A53_827319
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mov x0, #ERRATA_APPLIES
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ret
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#else
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mov x1, #0x02
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b cpu_rev_var_ls
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#endif
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endfunc check_errata_827319
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/*
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* Errata workaround for Cortex A53 Errata #835769.
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* This applies to revisions <= r0p4 of Cortex A53.
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* This workaround is statically enabled at build time.
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*/
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func check_errata_835769
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cmp x0, #0x04
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b.hi errata_not_applies
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/*
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* Fix potentially available for revisions r0p2, r0p3 and r0p4.
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* If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit.
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*/
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cmp x0, #0x01
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mov x0, #ERRATA_APPLIES
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b.ls exit_check_errata_835769
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/* Load REVIDR. */
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mrs x1, revidr_el1
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/* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */
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tbz x1, #7, exit_check_errata_835769
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errata_not_applies:
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mov x0, #ERRATA_NOT_APPLIES
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exit_check_errata_835769:
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ret
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endfunc check_errata_835769
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/* ---------------------------------------------------------------------
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* Disable the cache non-temporal hint.
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*
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* This ignores the Transient allocation hint in the MAIR and treats
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* allocations the same as non-transient allocation types. As a result,
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* the LDNP and STNP instructions in AArch64 behave the same as the
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* equivalent LDP and STP instructions.
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*
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* This is relevant only for revisions <= r0p3 of Cortex-A53.
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* From r0p4 and onwards, the bit to disable the hint is enabled by
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* default at reset.
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*
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------------------------
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*/
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func errata_a53_836870_wa
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/*
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* Compare x0 against revision r0p3
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*/
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mov x17, x30
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bl check_errata_836870
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cbz x0, 1f
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mrs x1, CORTEX_A53_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH
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msr CORTEX_A53_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a53_836870_wa
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func check_errata_836870
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mov x1, #0x03
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b cpu_rev_var_ls
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endfunc check_errata_836870
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/*
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* Errata workaround for Cortex A53 Errata #843419.
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* This applies to revisions <= r0p4 of Cortex A53.
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* This workaround is statically enabled at build time.
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*/
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func check_errata_843419
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mov x1, #ERRATA_APPLIES
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mov x2, #ERRATA_NOT_APPLIES
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cmp x0, #0x04
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csel x0, x1, x2, ls
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/*
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* Fix potentially available for revision r0p4.
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* If r0p4 check for fix in REVIDR, else exit.
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*/
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b.ne exit_check_errata_843419
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/* Load REVIDR. */
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mrs x3, revidr_el1
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/* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */
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tbz x3, #8, exit_check_errata_843419
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mov x0, x2
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exit_check_errata_843419:
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ret
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endfunc check_errata_843419
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/* --------------------------------------------------
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* Errata Workaround for Cortex A53 Errata #855873.
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*
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* This applies only to revisions >= r0p3 of Cortex A53.
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* Earlier revisions of the core are affected as well, but don't
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* have the chicken bit in the CPUACTLR register. It is expected that
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* the rich OS takes care of that, especially as the workaround is
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* shared with other erratas in those revisions of the CPU.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a53_855873_wa
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/*
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* Compare x0 against revision r0p3 and higher
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*/
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mov x17, x30
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bl check_errata_855873
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cbz x0, 1f
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mrs x1, CORTEX_A53_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
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msr CORTEX_A53_CPUACTLR_EL1, x1
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1:
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ret x17
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endfunc errata_a53_855873_wa
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func check_errata_855873
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mov x1, #0x03
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b cpu_rev_var_hs
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endfunc check_errata_855873
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/* --------------------------------------------------
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* Errata workaround for Cortex A53 Errata #1530924.
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* This applies to all revisions of Cortex A53.
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* --------------------------------------------------
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*/
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func check_errata_1530924
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#if ERRATA_A53_1530924
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_1530924
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A53.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func cortex_a53_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A53_826319
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mov x0, x18
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bl errata_a53_826319_wa
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#endif
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#if ERRATA_A53_836870
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mov x0, x18
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bl errata_a53_836870_wa
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#endif
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#if ERRATA_A53_855873
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mov x0, x18
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bl errata_a53_855873_wa
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A53_ECTLR_EL1
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orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
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msr CORTEX_A53_ECTLR_EL1, x0
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isb
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ret x19
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endfunc cortex_a53_reset_func
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func cortex_a53_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a53_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a53_disable_smp
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endfunc cortex_a53_core_pwr_dwn
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func cortex_a53_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a53_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a53_disable_smp
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endfunc cortex_a53_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A53. Must follow AAPCS.
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*/
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func cortex_a53_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A53_819472, cortex_a53, 819472
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report_errata ERRATA_A53_824069, cortex_a53, 824069
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report_errata ERRATA_A53_826319, cortex_a53, 826319
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report_errata ERRATA_A53_827319, cortex_a53, 827319
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report_errata ERRATA_A53_835769, cortex_a53, 835769
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report_errata ERRATA_A53_836870, cortex_a53, 836870
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report_errata ERRATA_A53_843419, cortex_a53, 843419
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report_errata ERRATA_A53_855873, cortex_a53, 855873
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report_errata ERRATA_A53_1530924, cortex_a53, 1530924
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a53_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a53 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a53_regs, "aS"
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cortex_a53_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \
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"cpuactlr_el1", ""
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func cortex_a53_cpu_reg_dump
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adr x6, cortex_a53_regs
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mrs x8, CORTEX_A53_ECTLR_EL1
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mrs x9, CORTEX_A53_MERRSR_EL1
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mrs x10, CORTEX_A53_L2MERRSR_EL1
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mrs x11, CORTEX_A53_CPUACTLR_EL1
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ret
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endfunc cortex_a53_cpu_reg_dump
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declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
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cortex_a53_reset_func, \
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cortex_a53_core_pwr_dwn, \
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cortex_a53_cluster_pwr_dwn
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