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e31fb0fa1b
Adding load, authentication, and transfer functionality from FVP R BL1 to BL33, which will be the partner runtime code. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I293cad09739dacac0d20dd57c1d98178dbe84d40
272 lines
8.5 KiB
C
272 lines
8.5 KiB
C
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FVP_R_PLATFORM_DEF_H
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#define FVP_R_PLATFORM_DEF_H
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#define PLAT_V2M_OFFSET 0x80000000
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#define BL33_IMAGE_DESC { \
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.image_id = BL33_IMAGE_ID, \
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \
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VERSION_2, image_info_t, 0), \
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.image_info.image_base = PLAT_ARM_DRAM1_BASE + 0x1000, \
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.image_info.image_max_size = UL(0x3ffff000), \
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \
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VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\
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.ep_info.pc = PLAT_ARM_DRAM1_BASE + 0x1000, \
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.ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), \
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}
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#include "../fvp_r_def.h"
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#include <drivers/arm/tzc400.h>
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#include <lib/utils_def.h>
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#include <plat/arm/board/common/v2m_def.h>
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/* These are referenced by arm_def.h #included next, so #define first. */
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#define PLAT_ARM_TRUSTED_ROM_BASE UL(0x80000000)
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#define PLAT_ARM_TRUSTED_SRAM_BASE UL(0x84000000)
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#define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x86000000)
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#define PLAT_ARM_DRAM1_BASE ULL(0x0)
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#define PLAT_ARM_DRAM2_BASE ULL(0x080000000)
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#define PLAT_HW_CONFIG_DTB_BASE ULL(0x12000000)
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#define PLAT_ARM_SYS_CNTCTL_BASE UL(0xaa430000)
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#define PLAT_ARM_SYS_CNTREAD_BASE UL(0xaa800000)
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#define PLAT_ARM_SYS_TIMCTL_BASE UL(0xaa810000)
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#define PLAT_ARM_SYS_CNT_BASE_S UL(0xaa820000)
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#define PLAT_ARM_SYS_CNT_BASE_NS UL(0xaa830000)
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#define PLAT_ARM_SP805_TWDG_BASE UL(0xaa490000)
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#include <plat/arm/common/arm_def.h>
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#include <plat/common/common_def.h>
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/* Required to create plat_regions: */
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#define MIN_LVL_BLOCK_DESC U(1)
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/* Required platform porting definitions */
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#define PLATFORM_CORE_COUNT (U(FVP_R_CLUSTER_COUNT) * \
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U(FVP_R_MAX_CPUS_PER_CLUSTER) * \
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U(FVP_R_MAX_PE_PER_CPU))
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#define PLAT_NUM_PWR_DOMAINS (U(FVP_R_CLUSTER_COUNT) + \
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PLATFORM_CORE_COUNT + U(1))
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2
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/*
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* Other platform porting definitions are provided by included headers
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*/
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/*
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* Required ARM standard platform porting definitions
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*/
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#define PLAT_ARM_CLUSTER_COUNT U(FVP_R_CLUSTER_COUNT)
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#define PLAT_ARM_DRAM1_SIZE ULL(0x7fffffff)
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#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */
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#define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */
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#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */
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/* These two are defined thus in arm_def.h, but doesn't seem to see it... */
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#define PLAT_BL1_RO_LIMIT (BL1_RO_BASE \
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+ PLAT_ARM_TRUSTED_ROM_SIZE)
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#define PLAT_ARM_SYS_CNTCTL_BASE UL(0xaa430000)
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#define PLAT_ARM_SYS_CNTREAD_BASE UL(0xaa800000)
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#define PLAT_ARM_SYS_TIMCTL_BASE UL(0xaa810000)
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#define PLAT_ARM_SYS_CNT_BASE_S UL(0xaa820000)
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#define PLAT_ARM_SYS_CNT_BASE_NS UL(0xaa830000)
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#define PLAT_ARM_SP805_TWDG_BASE UL(0xaa490000)
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/* virtual address used by dynamic mem_protect for chunk_base */
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#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
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/* No SCP in FVP_R */
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0)
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#define PLAT_ARM_DRAM2_SIZE UL(0x80000000)
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#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000)
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#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \
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PLAT_HW_CONFIG_DTB_BASE, \
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PLAT_HW_CONFIG_DTB_SIZE, \
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MT_MEMORY | MT_RO | MT_NS)
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#define V2M_FVP_R_SYSREGS_BASE UL(0x9c010000)
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/*
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* Load address of BL33 for this platform port,
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* U-Boot specifically must be loaded at a 4K aligned address.
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*/
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#define PLAT_ARM_NS_IMAGE_BASE (PLAT_ARM_DRAM1_BASE + 0x1000)
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/*
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* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
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* plat_arm_mmap array defined for each BL stage.
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*/
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#if !USE_ROMLIB
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# define PLAT_ARM_MMAP_ENTRIES 11
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# define MAX_XLAT_TABLES 5
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#else
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# define PLAT_ARM_MMAP_ENTRIES 12
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# define MAX_XLAT_TABLES 6
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#endif
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# define N_MPU_REGIONS 16 /* number of MPU regions */
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# define ALL_MPU_EL2_REGIONS_USED 0xffffffff
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/* this is the PRENR_EL2 value if all MPU regions are in use */
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/*
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* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
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* plus a little space for growth.
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*/
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#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000)
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/*
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* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
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*/
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#if USE_ROMLIB
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
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#define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0x6000)
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#else
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#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
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#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
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#define FVP_R_BL2_ROMLIB_OPTIMIZATION UL(0)
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#endif
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/*
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* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
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* little space for growth.
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*/
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#if TRUSTED_BOARD_BOOT
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#if COT_DESC_IN_DTB
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# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_R_BL2_ROMLIB_OPTIMIZATION)
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#else
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# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_R_BL2_ROMLIB_OPTIMIZATION)
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#endif
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#else
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# define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_R_BL2_ROMLIB_OPTIMIZATION)
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#endif
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/*
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* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
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* calculated using the current BL31 PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW
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*/
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#define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000)
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/*
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* Size of cacheable stacks
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*/
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#if defined(IMAGE_BL1)
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# if TRUSTED_BOARD_BOOT
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# define PLATFORM_STACK_SIZE UL(0x1000)
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# else
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# define PLATFORM_STACK_SIZE UL(0x500)
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# endif
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#endif
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/*
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* These nominally reserve the last block of flash for PSCI MEM PROTECT flag,
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* but no PSCI in FVP_R platform, so reserve nothing:
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*/
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#define PLAT_ARM_FLASH_IMAGE_BASE (PLAT_ARM_DRAM1_BASE + UL(0x40000000))
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (PLAT_ARM_DRAM1_SIZE - UL(0x40000000))
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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/*
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* PL011 related constants
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*/
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#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
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#define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
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#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
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#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
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/* CCI related constants */
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#define PLAT_FVP_R_CCI400_BASE UL(0xac090000)
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#define PLAT_FVP_R_CCI400_CLUS0_SL_PORT 3
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#define PLAT_FVP_R_CCI400_CLUS1_SL_PORT 4
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/* CCI-500/CCI-550 on Base platform */
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#define PLAT_FVP_R_CCI5XX_BASE UL(0xaa000000)
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#define PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT 5
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#define PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT 6
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/* CCN related constants. Only CCN 502 is currently supported */
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#define PLAT_ARM_CCN_BASE UL(0xae000000)
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#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11
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/* System timer related constants */
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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/* Mailbox base address */
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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/* TrustZone controller related constants
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*
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* Currently only filters 0 and 2 are connected on Base FVP_R.
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* Filter 0 : CPU clusters (no access to DRAM by default)
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* Filter 1 : not connected
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* Filter 2 : LCDs (access to VRAM allowed by default)
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* Filter 3 : not connected
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* Programming unconnected filters will have no effect at the
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* moment. These filter could, however, be connected in future.
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* So care should be taken not to configure the unused filters.
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*
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* Allow only non-secure access to all DRAM to supported devices.
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* Give access to the CPUs and Virtio. Some devices
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* would normally use the default ID so allow that too.
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*/
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#define PLAT_ARM_TZC_BASE UL(0xaa4a0000)
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#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
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#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
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TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_DEFAULT) | \
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TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_PCI) | \
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TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_AP) | \
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TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO) | \
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TZC_REGION_ACCESS_RDWR(FVP_R_NSAID_VIRTIO_OLD))
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/*
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* GIC related constants to cater for both GICv2 and GICv3 instances of an
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* FVP_R. They could be overridden at runtime in case the FVP_R implements the
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* legacy VE memory map.
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*/
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#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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#define PLAT_ARM_GICR_BASE BASE_GICR_BASE
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#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
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#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
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PLAT_SP_IMAGE_NS_BUF_SIZE)
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#define PLAT_SP_PRI PLAT_RAS_PRI
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/*
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* Physical and virtual address space limits for MPU in AARCH64 & AARCH32 modes
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
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#define ARM_SOC_CONTINUATION_SHIFT U(24)
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#define ARM_SOC_IDENTIFICATION_SHIFT U(16)
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#endif /* FVP_R_PLATFORM_DEF_H */
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