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e2bf57f841
Some assembly files containing macros are included like header files into other assembly files. This will cause assembler errors if they are included multiple times. Add header guards to assembly macro files to avoid assembler errors. Change-Id: Ia632e767ed7df7bf507b294982b8d730a6f8fe69
86 lines
2.8 KiB
ArmAsm
86 lines
2.8 KiB
ArmAsm
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_MACROS_S__
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#define __CPU_MACROS_S__
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#include <arch.h>
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#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
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(MIDR_PN_MASK << MIDR_PN_SHIFT)
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/*
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* Define the offsets to the fields in cpu_ops structure.
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*/
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.struct 0
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CPU_MIDR: /* cpu_ops midr */
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.space 8
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/* Reset fn is needed in BL at reset vector */
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#if IMAGE_BL1 || IMAGE_BL31
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CPU_RESET_FUNC: /* cpu_ops reset_func */
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.space 8
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#endif
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#if IMAGE_BL31 /* The power down core and cluster is needed only in BL3-1 */
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CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
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.space 8
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CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
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.space 8
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#endif
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#if (IMAGE_BL31 && CRASH_REPORTING)
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CPU_REG_DUMP: /* cpu specific register dump for crash reporting */
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.space 8
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#endif
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CPU_OPS_SIZE = .
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/*
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* Convenience macro to declare cpu_ops structure.
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* Make sure the structure fields are as per the offsets
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* defined above.
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*/
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.macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0
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.section cpu_ops, "a"; .align 3
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.type cpu_ops_\_name, %object
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.quad \_midr
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#if IMAGE_BL1 || IMAGE_BL31
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.if \_noresetfunc
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.quad 0
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.else
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.quad \_name\()_reset_func
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.endif
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#endif
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#if IMAGE_BL31
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.quad \_name\()_core_pwr_dwn
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.quad \_name\()_cluster_pwr_dwn
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#endif
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#if (IMAGE_BL31 && CRASH_REPORTING)
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.quad \_name\()_cpu_reg_dump
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#endif
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.endm
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#endif /* __CPU_MACROS_S__ */
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