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e290a8fcbc
This patch fixes an issue when secure world timing information can be leaked because Secure Cycle Counter is not disabled. For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR_EL0.DP bit. 'include\aarch64\arch.h' header file was tided up and new ARMv8.5-PMU related definitions were added. Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> |
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| .. | ||
| bl_aux_params | ||
| cpus | ||
| el3_runtime | ||
| extensions | ||
| libc | ||
| libfdt | ||
| pmf | ||
| psci | ||
| sprt | ||
| xlat_tables | ||
| zlib | ||
| bakery_lock.h | ||
| cassert.h | ||
| coreboot.h | ||
| mmio.h | ||
| object_pool.h | ||
| optee_utils.h | ||
| runtime_instr.h | ||
| semihosting.h | ||
| smccc.h | ||
| spinlock.h | ||
| utils.h | ||
| utils_def.h | ||