mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 01:24:27 +00:00
e290a8fcbc
This patch fixes an issue when secure world timing information can be leaked because Secure Cycle Counter is not disabled. For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR_EL0.DP bit. 'include\aarch64\arch.h' header file was tided up and new ARMv8.5-PMU related definitions were added. Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
403 lines
15 KiB
ArmAsm
403 lines
15 KiB
ArmAsm
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef EL3_COMMON_MACROS_S
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#define EL3_COMMON_MACROS_S
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#include <arch.h>
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#include <asm_macros.S>
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/*
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* Helper macro to initialise EL3 registers we care about.
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*/
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.macro el3_arch_init_common
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/* ---------------------------------------------------------------------
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* SCTLR_EL3 has already been initialised - read current value before
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* modifying.
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*
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* SCTLR_EL3.I: Enable the instruction cache.
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*
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* SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
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* exception is generated if a load or store instruction executed at
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* EL3 uses the SP as the base address and the SP is not aligned to a
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* 16-byte boundary.
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*
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* SCTLR_EL3.A: Enable Alignment fault checking. All instructions that
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* load or store one or more registers have an alignment check that the
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* address being accessed is aligned to the size of the data element(s)
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* being accessed.
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* ---------------------------------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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#ifdef IMAGE_BL31
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/* ---------------------------------------------------------------------
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* Initialise the per-cpu cache pointer to the CPU.
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* This is done early to enable crash reporting to have access to crash
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* stack. Since crash reporting depends on cpu_data to report the
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* unhandled exception, not doing so can lead to recursive exceptions
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* due to a NULL TPIDR_EL3.
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* ---------------------------------------------------------------------
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*/
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bl init_cpu_data_ptr
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#endif /* IMAGE_BL31 */
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/* ---------------------------------------------------------------------
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* Initialise SCR_EL3, setting all fields rather than relying on hw.
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* All fields are architecturally UNKNOWN on reset. The following fields
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* do not change during the TF lifetime. The remaining fields are set to
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* zero here but are updated ahead of transitioning to a lower EL in the
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* function cm_init_context_common().
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*
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* SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
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* EL2, EL1 and EL0 are not trapped to EL3.
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*
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* SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
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* EL2, EL1 and EL0 are not trapped to EL3.
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*
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* SCR_EL3.SIF: Set to one to disable instruction fetches from
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* Non-secure memory.
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*
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* SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
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* both Security states and both Execution states.
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*
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* SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
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* to EL3 when executing at any EL.
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*
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* SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature,
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* disable traps to EL3 when accessing key registers or using pointer
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* authentication instructions from lower ELs.
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \
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& ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT))
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#if CTX_INCLUDE_PAUTH_REGS
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/*
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* If the pointer authentication registers are saved during world
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* switches, enable pointer authentication everywhere, as it is safe to
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* do so.
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*/
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orr x0, x0, #(SCR_API_BIT | SCR_APK_BIT)
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#endif
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msr scr_el3, x0
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/* ---------------------------------------------------------------------
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* Initialise MDCR_EL3, setting all fields rather than relying on hw.
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* Some fields are architecturally UNKNOWN on reset.
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*
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* MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
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* Debug exceptions, other than Breakpoint Instruction exceptions, are
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* disabled from all ELs in Secure state.
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*
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* MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
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* privileged debug from S-EL1.
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*
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* MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
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* access to the powerdown debug registers do not trap to EL3.
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*
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* MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
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* debug registers, other than those registers that are controlled by
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* MDCR_EL3.TDOSA.
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*
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* MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
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* accesses to all Performance Monitors registers do not trap to EL3.
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*
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* MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is
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* prohibited in Secure state. This bit is RES0 in versions of the
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* architecture earlier than ARMv8.5, setting it to 1 doesn't have any
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* effect on them.
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
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MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \
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~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT))
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msr mdcr_el3, x0
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/* ---------------------------------------------------------------------
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* Initialise PMCR_EL0 setting all fields rather than relying
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* on hw. Some fields are architecturally UNKNOWN on reset.
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*
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* PMCR_EL0.LP: Set to one so that event counter overflow, that
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* is recorded in PMOVSCLR_EL0[0-30], occurs on the increment
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* that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU
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* is implemented. This bit is RES0 in versions of the architecture
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* earlier than ARMv8.5, setting it to 1 doesn't have any effect
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* on them.
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*
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* PMCR_EL0.LC: Set to one so that cycle counter overflow, that
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* is recorded in PMOVSCLR_EL0[31], occurs on the increment
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* that changes PMCCNTR_EL0[63] from 1 to 0.
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*
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* PMCR_EL0.DP: Set to one so that the cycle counter,
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* PMCCNTR_EL0 does not count when event counting is prohibited.
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*
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* PMCR_EL0.X: Set to zero to disable export of events.
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*
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* PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0
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* counts on every clock cycle.
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \
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PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \
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~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT))
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msr pmcr_el0, x0
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/* ---------------------------------------------------------------------
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* Enable External Aborts and SError Interrupts now that the exception
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* vectors have been setup.
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* ---------------------------------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------------------------------
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* Initialise CPTR_EL3, setting all fields rather than relying on hw.
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* All fields are architecturally UNKNOWN on reset.
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*
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* CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1,
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* CPTR_EL2, CPACR, or HCPTR do not trap to EL3.
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*
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* CPTR_EL3.TTA: Set to zero so that System register accesses to the
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* trace registers do not trap to EL3.
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*
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* CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
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* by Advanced SIMD, floating-point or SVE instructions (if implemented)
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* do not trap to EL3.
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*/
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mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
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msr cptr_el3, x0
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/*
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* If Data Independent Timing (DIT) functionality is implemented,
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* always enable DIT in EL3
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*/
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
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cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
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bne 1f
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mov x0, #DIT_BIT
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msr DIT, x0
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1:
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.endm
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/* -----------------------------------------------------------------------------
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* This is the super set of actions that need to be performed during a cold boot
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* or a warm boot in EL3. This code is shared by BL1 and BL31.
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*
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* This macro will always perform reset handling, architectural initialisations
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* and stack setup. The rest of the actions are optional because they might not
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* be needed, depending on the context in which this macro is called. This is
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* why this macro is parameterised ; each parameter allows to enable/disable
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* some actions.
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*
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* _init_sctlr:
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* Whether the macro needs to initialise SCTLR_EL3, including configuring
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* the endianness of data accesses.
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*
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* _warm_boot_mailbox:
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* Whether the macro needs to detect the type of boot (cold/warm). The
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* detection is based on the platform entrypoint address : if it is zero
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* then it is a cold boot, otherwise it is a warm boot. In the latter case,
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* this macro jumps on the platform entrypoint address.
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*
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* _secondary_cold_boot:
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* Whether the macro needs to identify the CPU that is calling it: primary
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* CPU or secondary CPU. The primary CPU will be allowed to carry on with
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* the platform initialisations, while the secondaries will be put in a
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* platform-specific state in the meantime.
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*
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* If the caller knows this macro will only be called by the primary CPU
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* then this parameter can be defined to 0 to skip this step.
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*
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* _init_memory:
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* Whether the macro needs to initialise the memory.
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*
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* _init_c_runtime:
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* Whether the macro needs to initialise the C runtime environment.
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*
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* _exception_vectors:
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* Address of the exception vectors to program in the VBAR_EL3 register.
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* -----------------------------------------------------------------------------
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*/
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.macro el3_entrypoint_common \
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_init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
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_init_memory, _init_c_runtime, _exception_vectors
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.if \_init_sctlr
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/* -------------------------------------------------------------
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* This is the initialisation of SCTLR_EL3 and so must ensure
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* that all fields are explicitly set rather than relying on hw.
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* Some fields reset to an IMPLEMENTATION DEFINED value and
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* others are architecturally UNKNOWN on reset.
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*
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* SCTLR.EE: Set the CPU endianness before doing anything that
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* might involve memory reads or writes. Set to zero to select
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* Little Endian.
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*
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* SCTLR_EL3.WXN: For the EL3 translation regime, this field can
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* force all memory regions that are writeable to be treated as
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* XN (Execute-never). Set to zero so that this control has no
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* effect on memory access permissions.
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*
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* SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
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*
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* SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
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*
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* SCTLR.DSSBS: Set to zero to disable speculation store bypass
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* safe behaviour upon exception entry to EL3.
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* -------------------------------------------------------------
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*/
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mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
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| SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT))
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msr sctlr_el3, x0
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isb
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.endif /* _init_sctlr */
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.if \_warm_boot_mailbox
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/* -------------------------------------------------------------
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* This code will be executed for both warm and cold resets.
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* Now is the time to distinguish between the two.
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* Query the platform entrypoint address and if it is not zero
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* then it means it is a warm boot so jump to this address.
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* -------------------------------------------------------------
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*/
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bl plat_get_my_entrypoint
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cbz x0, do_cold_boot
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br x0
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do_cold_boot:
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.endif /* _warm_boot_mailbox */
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/* ---------------------------------------------------------------------
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* Set the exception vectors.
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* ---------------------------------------------------------------------
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*/
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adr x0, \_exception_vectors
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msr vbar_el3, x0
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isb
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/* ---------------------------------------------------------------------
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* It is a cold boot.
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* Perform any processor specific actions upon reset e.g. cache, TLB
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* invalidations etc.
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* ---------------------------------------------------------------------
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*/
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bl reset_handler
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el3_arch_init_common
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.if \_secondary_cold_boot
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/* -------------------------------------------------------------
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* Check if this is a primary or secondary CPU cold boot.
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* The primary CPU will set up the platform while the
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* secondaries are placed in a platform-specific state until the
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* primary CPU performs the necessary actions to bring them out
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* of that state and allows entry into the OS.
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* -------------------------------------------------------------
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*/
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bl plat_is_my_cpu_primary
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cbnz w0, do_primary_cold_boot
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/* This is a cold boot on a secondary CPU */
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bl plat_secondary_cold_boot_setup
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/* plat_secondary_cold_boot_setup() is not supposed to return */
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bl el3_panic
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do_primary_cold_boot:
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.endif /* _secondary_cold_boot */
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/* ---------------------------------------------------------------------
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* Initialize memory now. Secondary CPU initialization won't get to this
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* point.
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* ---------------------------------------------------------------------
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*/
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.if \_init_memory
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bl platform_mem_init
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.endif /* _init_memory */
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/* ---------------------------------------------------------------------
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* Init C runtime environment:
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* - Zero-initialise the NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section (if any).
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* - Relocate the data section from ROM to RAM, if required.
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* ---------------------------------------------------------------------
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*/
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.if \_init_c_runtime
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#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3)
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/* -------------------------------------------------------------
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* Invalidate the RW memory used by the BL31 image. This
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* includes the data and NOBITS sections. This is done to
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* safeguard against possible corruption of this memory by
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* dirty cache lines in a system cache as a result of use by
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* an earlier boot loader stage.
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* -------------------------------------------------------------
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*/
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adrp x0, __RW_START__
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add x0, x0, :lo12:__RW_START__
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adrp x1, __RW_END__
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add x1, x1, :lo12:__RW_END__
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sub x1, x1, x0
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bl inv_dcache_range
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#endif
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adrp x0, __BSS_START__
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add x0, x0, :lo12:__BSS_START__
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adrp x1, __BSS_END__
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add x1, x1, :lo12:__BSS_END__
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sub x1, x1, x0
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bl zeromem
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#if USE_COHERENT_MEM
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adrp x0, __COHERENT_RAM_START__
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add x0, x0, :lo12:__COHERENT_RAM_START__
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adrp x1, __COHERENT_RAM_END_UNALIGNED__
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add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
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sub x1, x1, x0
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bl zeromem
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#endif
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#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM)
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adrp x0, __DATA_RAM_START__
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add x0, x0, :lo12:__DATA_RAM_START__
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adrp x1, __DATA_ROM_START__
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add x1, x1, :lo12:__DATA_ROM_START__
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adrp x2, __DATA_RAM_END__
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add x2, x2, :lo12:__DATA_RAM_END__
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sub x2, x2, x0
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bl memcpy16
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#endif
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.endif /* _init_c_runtime */
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/* ---------------------------------------------------------------------
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* Use SP_EL0 for the C runtime stack.
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* ---------------------------------------------------------------------
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*/
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msr spsel, #0
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/* ---------------------------------------------------------------------
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* Allocate a stack whose memory will be marked as Normal-IS-WBWA when
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* the MMU is enabled. There is no risk of reading stale stack memory
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* after enabling the MMU as only the primary CPU is running at the
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* moment.
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* ---------------------------------------------------------------------
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*/
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bl plat_set_my_stack
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#if STACK_PROTECTOR_ENABLED
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.if \_init_c_runtime
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bl update_stack_protector_canary
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.endif /* _init_c_runtime */
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#endif
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.endm
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#endif /* EL3_COMMON_MACROS_S */
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