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db9ee83432
The errata framework has a helper to invoke workarounds, complete with a cpu rev_var check. We can use that directly instead of the apply_cpu_pwr_dwn_errata to save on some code, as well as an extra branch. It's also more readable. Also, apply_erratum invocation in cpu files don't need to check the rev_var as that was already done by the cpu_ops dispatcher for us to end up in the file. Finally, X2 erratum 2768515 only applies in the powerdown sequence, i.e. at runtime. It doesn't achieve anything at reset, so we can label it accordingly. Change-Id: I02f9dd7d0619feb54c870938ea186be5e3a6ca7b Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
314 lines
10 KiB
ArmAsm
314 lines
10 KiB
ArmAsm
/*
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* Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <cortex_a57.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func cortex_a57_disable_dcache
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sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
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isb
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ret
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endfunc cortex_a57_disable_dcache
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/* ---------------------------------------------
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* Disable all types of L2 prefetches.
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* ---------------------------------------------
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*/
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func cortex_a57_disable_l2_prefetch
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mrs x0, CORTEX_A57_ECTLR_EL1
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orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
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mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK
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orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK
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bic x0, x0, x1
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msr CORTEX_A57_ECTLR_EL1, x0
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isb
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dsb ish
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ret
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endfunc cortex_a57_disable_l2_prefetch
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a57_disable_smp
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sysreg_bit_clear CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT
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ret
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endfunc cortex_a57_disable_smp
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/* ---------------------------------------------
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* Disable debug interfaces
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* ---------------------------------------------
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*/
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func cortex_a57_disable_ext_debug
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mov x0, #1
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msr osdlr_el1, x0
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isb
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apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169, NO_GET_CPU_REV
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dsb sy
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ret
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endfunc cortex_a57_disable_ext_debug
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/*
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* Disable the over-read from the LDNP/STNP instruction. The SDEN doesn't
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* provide and erratum number, so assign it an obvious 1
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*/
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workaround_reset_start cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
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workaround_reset_end cortex_a57, ERRATUM(1)
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check_erratum_ls cortex_a57, ERRATUM(1), CPU_REV(1, 2)
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workaround_reset_start cortex_a57, ERRATUM(806969), ERRATA_A57_806969
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
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workaround_reset_end cortex_a57, ERRATUM(806969)
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check_erratum_ls cortex_a57, ERRATUM(806969), CPU_REV(0, 0)
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/* erratum always worked around, but report it correctly */
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check_erratum_ls cortex_a57, ERRATUM(813419), CPU_REV(0, 0)
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add_erratum_entry cortex_a57, ERRATUM(813419), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET
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workaround_reset_start cortex_a57, ERRATUM(813420), ERRATA_A57_813420
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
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workaround_reset_end cortex_a57, ERRATUM(813420)
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check_erratum_ls cortex_a57, ERRATUM(813420), CPU_REV(0, 0)
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workaround_reset_start cortex_a57, ERRATUM(814670), ERRATA_A57_814670
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION
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workaround_reset_end cortex_a57, ERRATUM(814670)
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check_erratum_ls cortex_a57, ERRATUM(814670), CPU_REV(0, 0)
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workaround_runtime_start cortex_a57, ERRATUM(817169), ERRATA_A57_817169, CORTEX_A57_MIDR
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/* Invalidate any TLB address */
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mov x0, #0
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tlbi vae3, x0
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workaround_runtime_end cortex_a57, ERRATUM(817169), NO_ISB
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check_erratum_ls cortex_a57, ERRATUM(817169), CPU_REV(0, 1)
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workaround_reset_start cortex_a57, ERRATUM(826974), ERRATA_A57_826974
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
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workaround_reset_end cortex_a57, ERRATUM(826974)
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check_erratum_ls cortex_a57, ERRATUM(826974), CPU_REV(1, 1)
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workaround_reset_start cortex_a57, ERRATUM(826977), ERRATA_A57_826977
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
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workaround_reset_end cortex_a57, ERRATUM(826977)
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check_erratum_ls cortex_a57, ERRATUM(826977), CPU_REV(1, 1)
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workaround_reset_start cortex_a57, ERRATUM(828024), ERRATA_A57_828024
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mrs x1, CORTEX_A57_CPUACTLR_EL1
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/*
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* Setting the relevant bits in CPUACTLR_EL1 has to be done in 2
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* instructions here because the resulting bitmask doesn't fit in a
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* 16-bit value so it cannot be encoded in a single instruction.
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*/
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orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
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orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \
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CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING)
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msr CORTEX_A57_CPUACTLR_EL1, x1
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workaround_reset_end cortex_a57, ERRATUM(828024)
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check_erratum_ls cortex_a57, ERRATUM(828024), CPU_REV(1, 1)
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workaround_reset_start cortex_a57, ERRATUM(829520), ERRATA_A57_829520
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
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workaround_reset_end cortex_a57, ERRATUM(829520)
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check_erratum_ls cortex_a57, ERRATUM(829520), CPU_REV(1, 2)
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workaround_reset_start cortex_a57, ERRATUM(833471), ERRATA_A57_833471
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
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workaround_reset_end cortex_a57, ERRATUM(833471)
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check_erratum_ls cortex_a57, ERRATUM(833471), CPU_REV(1, 2)
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workaround_reset_start cortex_a57, ERRATUM(859972), ERRATA_A57_859972
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH
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workaround_reset_end cortex_a57, ERRATUM(859972)
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check_erratum_ls cortex_a57, ERRATUM(859972), CPU_REV(1, 3)
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check_erratum_chosen cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537
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/* erratum has no workaround in the cpu. Generic code must take care */
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add_erratum_entry cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537, NO_APPLY_AT_RESET
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workaround_reset_start cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
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#if IMAGE_BL31
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override_vector_table wa_cve_2017_5715_mmu_vbar
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#endif
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workaround_reset_end cortex_a57, CVE(2017, 5715)
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check_erratum_chosen cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
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workaround_reset_start cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
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isb
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dsb sy
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workaround_reset_end cortex_a57, CVE(2018, 3639)
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check_erratum_chosen cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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workaround_reset_start cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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override_vector_table wa_cve_2017_5715_mmu_vbar
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#endif
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workaround_reset_end cortex_a57, CVE(2022, 23960)
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check_erratum_chosen cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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cpu_reset_func_start cortex_a57
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#if A57_ENABLE_NONCACHEABLE_LOAD_FWD
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/* Enable higher performance non-cacheable load forwarding */
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sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD
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#endif
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/* Enable the SMP bit. */
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sysreg_bit_set CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT
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cpu_reset_func_end cortex_a57
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func check_smccc_arch_workaround_3
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mov x0, #ERRATA_APPLIES
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ret
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endfunc check_smccc_arch_workaround_3
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A57.
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* ----------------------------------------------------
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*/
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func cortex_a57_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a57_disable_dcache
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a57_disable_l2_prefetch
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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bl cortex_a57_disable_smp
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a57_disable_ext_debug
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endfunc cortex_a57_core_pwr_dwn
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Cortex-A57.
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* -------------------------------------------------------
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*/
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func cortex_a57_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a57_disable_dcache
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/* ---------------------------------------------
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* Disable the L2 prefetches.
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* ---------------------------------------------
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*/
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bl cortex_a57_disable_l2_prefetch
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#if !SKIP_A57_L1_FLUSH_PWR_DWN
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/* -------------------------------------------------
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* Flush the L1 caches.
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* -------------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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#endif
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* -------------------------------------------------
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* Flush the L2 caches.
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* -------------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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bl cortex_a57_disable_smp
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/* ---------------------------------------------
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* Force the debug interfaces to be quiescent
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a57_disable_ext_debug
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endfunc cortex_a57_cluster_pwr_dwn
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/* ---------------------------------------------
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* This function provides cortex_a57 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a57_regs, "aS"
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cortex_a57_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", ""
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func cortex_a57_cpu_reg_dump
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adr x6, cortex_a57_regs
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mrs x8, CORTEX_A57_ECTLR_EL1
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mrs x9, CORTEX_A57_MERRSR_EL1
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mrs x10, CORTEX_A57_L2MERRSR_EL1
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ret
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endfunc cortex_a57_cpu_reg_dump
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declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \
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cortex_a57_reset_func, \
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check_erratum_cortex_a57_5715, \
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CPU_NO_EXTRA2_FUNC, \
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check_smccc_arch_workaround_3, \
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cortex_a57_core_pwr_dwn, \
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cortex_a57_cluster_pwr_dwn
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