Manish V Badarkhe e1b15b09a5 fix(gic600): implement workaround to forward highest priority interrupt ... If the interrupt being targeted is released from the CPU before the CLEAR command is sent to the CPU then a subsequent SET command may not be delivered in a finite time. To workaround this, issue an unblocking event by toggling GICR_CTLR.DPG* bits after clearing the cpu group enable (EnableGrp* bits of GIC CPU interface register) This fix is implemented as per the errata 2384374-part 2 workaround mentioned here: https://developer.arm.com/documentation/sden892601/latest/ Change-Id: I13926ceeb7740fa4c05cc5b43170e7ce49598f70 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>		2022-06-15 22:02:13 +01:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	Cleanup the code for TBBR CoT descriptors	2020-05-19 05:05:19 +01:00
cpu-specific-build-macros.rst	fix(gic600): implement workaround to forward highest priority interrupt	2022-06-15 22:02:13 +01:00
firmware-design.rst	docs(fvp): update loading addresses of HW_CONFIG	2022-04-28 07:09:53 +01:00
index.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
interrupt-framework-design.rst	Fix broken links to various sections across docs	2020-08-03 09:55:04 -05:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	docs(bl31): aarch64: RESET_TO_BL31_WITH_PARAMS	2022-04-29 22:54:34 +02:00
trusted-board-boot-build.rst	Mention COT build option in trusted-board-boot-build.rst	2020-03-12 17:11:26 +01:00
trusted-board-boot.rst	fix: remove "experimental" tag for stable features	2021-10-22 10:49:20 +01:00