mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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6704f425dd
Use the generic delay timer instead of having a specific platform file for configuring it. Change-Id: Ifa68b9c97cd96ae1190cee74d22d729af95e4537
135 lines
4.7 KiB
C
135 lines
4.7 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLAT_DEF_H__
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#define __PLAT_DEF_H__
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define CCI400_BASE 0xffb90000
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#define CCI400_SIZE 0x10000
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#define GIC400_BASE 0xffb70000
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#define GIC400_SIZE 0x10000
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#define STIME_BASE 0xff830000
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#define STIME_SIZE 0x10000
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#define CRU_BASE 0xff760000
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#define CRU_SIZE 0x10000
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#define GRF_BASE 0xff770000
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#define GRF_SIZE 0x10000
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#define SGRF_BASE 0xff740000
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#define SGRF_SIZE 0x10000
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#define PMU_BASE 0xff730000
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#define PMU_GRF_BASE 0xff738000
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#define PMU_SIZE 0x10000
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#define RK_INTMEM_BASE 0xff8c0000
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#define RK_INTMEM_SIZE 0x10000
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#define UART_DBG_BASE 0xff690000
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#define UART_DBG_SIZE 0x10000
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#define CRU_BASE 0xff760000
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#define PMUSRAM_BASE 0xff720000
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#define PMUSRAM_SIZE 0x10000
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#define PMUSRAM_RSIZE 0x1000
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#define DDR_PCTL_BASE 0xff610000
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#define DDR_PCTL_SIZE 0x10000
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#define DDR_PHY_BASE 0xff620000
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#define DDR_PHY_SIZE 0x10000
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#define SERVICE_BUS_BASE 0xffac0000
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#define SERVICE_BUS_SISE 0x50000
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#define COLD_BOOT_BASE 0xffff0000
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/**************************************************************************
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* UART related constants
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**************************************************************************/
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#define RK3368_UART2_BASE UART_DBG_BASE
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#define RK3368_BAUDRATE 115200
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#define RK3368_UART_CLOCK 24000000
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/******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 24000000
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/******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base rk_platform compatible GIC memory map */
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#define RK3368_GICD_BASE (GIC400_BASE + 0x1000)
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#define RK3368_GICC_BASE (GIC400_BASE + 0x2000)
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#define RK3368_GICR_BASE 0 /* no GICR in GIC-400 */
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/*****************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 3
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#define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 4
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/******************************************************************************
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* cpu up status
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******************************************************************************/
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#define PMU_CPU_HOTPLUG 0xdeadbeaf
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#define PMU_CPU_AUTO_PWRDN 0xabcdef12
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/******************************************************************************
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* sgi, ppi
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******************************************************************************/
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#define RK_IRQ_SEC_PHY_TIMER 29
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#define RK_IRQ_SEC_SGI_0 8
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#define RK_IRQ_SEC_SGI_1 9
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#define RK_IRQ_SEC_SGI_2 10
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#define RK_IRQ_SEC_SGI_3 11
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#define RK_IRQ_SEC_SGI_4 12
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#define RK_IRQ_SEC_SGI_5 13
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#define RK_IRQ_SEC_SGI_6 14
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#define RK_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define RK_G1S_IRQS (RK_IRQ_SEC_PHY_TIMER)
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#endif /* __PLAT_DEF_H__ */
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