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https://github.com/ARM-software/arm-trusted-firmware.git
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f3d3b316f8
Replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all upstream platforms. Change-Id: I3248f3f65a16dc5e9720012a05c35b9e3ba6abbe
80 lines
3 KiB
C
80 lines
3 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <xlat_tables.h>
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#include <tegra_def.h>
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/*******************************************************************************
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* The Tegra power domain tree has a single system level power domain i.e. a
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* single root node. The first entry in the power domain descriptor specifies
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* the number of power domains at the highest power level.
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*******************************************************************************
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*/
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const unsigned char tegra_power_domain_tree_desc[] = {
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/* No of root nodes */
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1,
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/* No of clusters */
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PLATFORM_CLUSTER_COUNT,
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/* No of CPU cores */
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PLATFORM_CORE_COUNT,
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};
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/* sets of MMIO ranges setup */
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#define MMIO_RANGE_0_ADDR 0x50000000
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#define MMIO_RANGE_1_ADDR 0x60000000
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#define MMIO_RANGE_2_ADDR 0x70000000
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#define MMIO_RANGE_SIZE 0x200000
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/*
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* Table of regions to map using the MMU.
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*/
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static const mmap_region_t tegra_mmap[] = {
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MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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{0}
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};
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/*******************************************************************************
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* Set up the pagetables as per the platform memory map & initialize the MMU
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******************************************************************************/
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const mmap_region_t *plat_get_mmio_map(void)
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{
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/* MMIO space */
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return tegra_mmap;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return 12000000;
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}
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