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https://github.com/ARM-software/arm-trusted-firmware.git
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1d0b990e9d
Use the generic delay timer instead of having a specific platform file for configuring it. Change-Id: If6b8f60bc04230f4b85b2bcc1b670fc65461214e
129 lines
5 KiB
C
129 lines
5 KiB
C
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MT8173_DEF_H__
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#define __MT8173_DEF_H__
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#if RESET_TO_BL31
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#error "MT8173 is incompatible with RESET_TO_BL31!"
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#endif
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#define MT8173_PRIMARY_CPU 0x0
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/* Register base address */
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#define IO_PHYS (0x10000000)
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#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
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#define SRAMROM_SEC_BASE (IO_PHYS + 0x1800)
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#define PERI_CON_BASE (IO_PHYS + 0x3000)
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#define GPIO_BASE (IO_PHYS + 0x5000)
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#define SPM_BASE (IO_PHYS + 0x6000)
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#define RGU_BASE (IO_PHYS + 0x7000)
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#define PMIC_WRAP_BASE (IO_PHYS + 0xD000)
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#define DEVAPC0_BASE (IO_PHYS + 0xE000)
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#define MCUCFG_BASE (IO_PHYS + 0x200000)
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#define APMIXED_BASE (IO_PHYS + 0x209000)
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#define TRNG_BASE (IO_PHYS + 0x20F000)
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#define CRYPT_BASE (IO_PHYS + 0x210000)
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#define MT_GIC_BASE (IO_PHYS + 0x220000)
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#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000)
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/* Aggregate of all devices in the first GB */
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#define MTK_DEV_RNG0_BASE IO_PHYS
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#define MTK_DEV_RNG0_SIZE 0x400000
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#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000)
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#define MTK_DEV_RNG1_SIZE 0x4000000
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/* SRAMROM related registers */
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#define SRAMROM_SEC_CTRL (SRAMROM_SEC_BASE + 0x4)
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#define SRAMROM_SEC_ADDR (SRAMROM_SEC_BASE + 0x8)
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/* DEVAPC0 related registers */
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#define DEVAPC0_MAS_SEC_0 (DEVAPC0_BASE + 0x500)
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#define DEVAPC0_APC_CON (DEVAPC0_BASE + 0xF00)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define MT8173_UART0_BASE (IO_PHYS + 0x01002000)
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#define MT8173_UART1_BASE (IO_PHYS + 0x01003000)
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#define MT8173_UART2_BASE (IO_PHYS + 0x01004000)
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#define MT8173_UART3_BASE (IO_PHYS + 0x01005000)
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#define MT8173_BAUDRATE (115200)
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#define MT8173_UART_CLOCK (26000000)
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 13000000
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base MTK_platform compatible GIC memory map */
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#define BASE_GICD_BASE (MT_GIC_BASE + 0x1000)
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#define BASE_GICC_BASE (MT_GIC_BASE + 0x2000)
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#define BASE_GICR_BASE 0 /* no GICR in GIC-400 */
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#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000)
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#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000)
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#define INT_POL_CTL0 0x10200620
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#define GIC_PRIVATE_SIGNALS (32)
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4
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#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3
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/*******************************************************************************
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* WDT related constants
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******************************************************************************/
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#define MTK_WDT_BASE (RGU_BASE + 0)
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#define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014)
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#define MTK_WDT_MODE_DUAL_MODE 0x0040
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#define MTK_WDT_MODE_IRQ 0x0008
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#define MTK_WDT_MODE_KEY 0x22000000
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#define MTK_WDT_MODE_EXTEN 0x0004
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#define MTK_WDT_SWRST_KEY 0x1209
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/* FIQ platform related define */
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#define MT_IRQ_SEC_SGI_0 8
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#define MT_IRQ_SEC_SGI_1 9
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#define MT_IRQ_SEC_SGI_2 10
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#define MT_IRQ_SEC_SGI_3 11
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#define MT_IRQ_SEC_SGI_4 12
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#define MT_IRQ_SEC_SGI_5 13
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#define MT_IRQ_SEC_SGI_6 14
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#define MT_IRQ_SEC_SGI_7 15
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#endif /* __MT8173_DEF_H__ */
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