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https://github.com/ARM-software/arm-trusted-firmware.git
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7a4a07078b
This patch allocates level 0 GPT at the top of SRAM for FVP. This helps to meet L0 GPT alignment requirements and prevent the occurrence of possible unused gaps in SRAM. Load addresses for FVP TB_FW, SOC_FW and TOS_FW DTBs are defined in fvp_fw_config.dts via ARM_BL_RAM_BASE macro. Change-Id: Iaa52e302373779d9fdbaf4e1ba40c10aa8d1f8bd Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
62 lines
1.4 KiB
Text
62 lines
1.4 KiB
Text
/*
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* Copyright (c) 2019-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/tbbr/tbbr_img_def.h>
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#include <platform_def.h>
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/* DTB load addresses */
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#define TB_SOC_FW_ADDR (ARM_BL_RAM_BASE + 0x300)
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#define TOS_FW_ADDR (ARM_BL_RAM_BASE + 0x500)
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/dts-v1/;
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/ {
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dtb-registry {
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compatible = "fconf,dyn_cfg-dtb_registry";
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tb_fw-config {
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load-address = <0x0 TB_SOC_FW_ADDR>;
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max-size = <0x1800>;
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id = <TB_FW_CONFIG_ID>;
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};
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hw-config {
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load-address = <0x0 0x07f00000>;
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max-size = <PLAT_ARM_HW_CONFIG_SIZE>;
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id = <HW_CONFIG_ID>;
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secondary-load-address = <0x0 0x82000000>;
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};
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/*
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* Load SoC and TOS firmware configs at the base of
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* non shared SRAM. The runtime checks ensure we don't
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* overlap BL2, BL31 or BL32. The NT firmware config
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* is loaded at base of DRAM.
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*/
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soc_fw-config {
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load-address = <0x0 TB_SOC_FW_ADDR>;
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max-size = <0x200>;
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id = <SOC_FW_CONFIG_ID>;
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};
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/* If required, SPD should enable loading of trusted OS fw config */
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#if defined(SPD_tspd) || defined(SPD_spmd)
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tos_fw-config {
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load-address = <0x0 TOS_FW_ADDR>;
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#if ENABLE_RME
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secondary-load-address = <0x0 0x7e00000>;
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#endif /* ENABLE_RME */
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max-size = <0xB00>;
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id = <TOS_FW_CONFIG_ID>;
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};
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#endif
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nt_fw-config {
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load-address = <0x0 0x80000000>;
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max-size = <0x200>;
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id = <NT_FW_CONFIG_ID>;
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};
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};
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};
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