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https://github.com/ARM-software/arm-trusted-firmware.git
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e0a8ce5d0d
Include all RCC, clocks and reset headers from stm32mp1_def.h which if exported to the firmware through platform_def.h. The same dependency removal is done in common code as well. Some useless includes are also removed in stm32_sdmmc2 driver. Change-Id: I731ea5775c3fdb7f7b0c388b93923ed5e84b8d3f Signed-off-by: Yann Gautier <yann.gautier@st.com>
111 lines
3.5 KiB
C
111 lines
3.5 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <drivers/arm/tzc400.h>
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#include <drivers/st/stm32mp1_clk.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <lib/mmio.h>
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/*******************************************************************************
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* Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
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* and allow Non-Secure masters full access.
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******************************************************************************/
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static void init_tzc400(void)
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{
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unsigned long long region_base, region_top;
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unsigned long long ddr_base = STM32MP_DDR_BASE;
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unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
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tzc400_init(STM32MP1_TZC_BASE);
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tzc400_disable_filters();
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/* Region 1 set to cover all DRAM at 0xC000_0000. Apply the
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* same configuration to all filters in the TZC.
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*/
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region_base = ddr_base;
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region_top = ddr_base + (ddr_size - 1U);
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tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
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region_base,
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region_top,
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TZC_REGION_S_RDWR,
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) |
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) |
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) |
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) |
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) |
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) |
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) |
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) |
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID));
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/* Raise an exception if a NS device tries to access secure memory */
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tzc400_set_action(TZC_ACTION_ERR);
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tzc400_enable_filters();
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}
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/*******************************************************************************
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* Initialize the TrustZone Controller.
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* Early initialization create only one region with full access to secure.
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* This setting is used before and during DDR initialization.
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******************************************************************************/
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static void early_init_tzc400(void)
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{
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if (stm32mp_clk_enable(TZC1) != 0) {
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ERROR("Cannot enable TZC1 clock\n");
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panic();
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}
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if (stm32mp_clk_enable(TZC2) != 0) {
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ERROR("Cannot enable TZC2 clock\n");
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panic();
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}
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tzc400_init(STM32MP1_TZC_BASE);
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tzc400_disable_filters();
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/*
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* Region 1 set to cover Non-Secure DRAM at 0x8000_0000. Apply the
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* same configuration to all filters in the TZC.
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*/
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tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
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STM32MP_DDR_BASE,
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STM32MP_DDR_BASE +
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(STM32MP_DDR_MAX_SIZE - 1U),
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TZC_REGION_S_RDWR,
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
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TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));
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/* Raise an exception if a NS device tries to access secure memory */
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tzc400_set_action(TZC_ACTION_ERR);
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tzc400_enable_filters();
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}
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/*******************************************************************************
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* Initialize the secure environment. At this moment only the TrustZone
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* Controller is initialized.
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******************************************************************************/
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void stm32mp1_arch_security_setup(void)
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{
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early_init_tzc400();
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}
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/*******************************************************************************
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* Initialize the secure environment. At this moment only the TrustZone
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* Controller is initialized.
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******************************************************************************/
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void stm32mp1_security_setup(void)
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{
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init_tzc400();
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}
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