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35cd9e8169
The GIC lowest priority values for each world depends on the number of priority values implemented in hardware. These constants currently defined in gic_common.h only meant to enumerate lowest possible architectural values. Since these values are not used in generic code or upstream platforms, and that general use of these constants can be wrong, remove these. Platforms should either define and use these as appropriate, or determine correct values at run time. Change-Id: I3805cea8ceb8a592b9eff681ea1b63b7496cec5f Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
101 lines
3.3 KiB
C
101 lines
3.3 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GIC_COMMON_H
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#define GIC_COMMON_H
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#include <utils_def.h>
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/*******************************************************************************
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* GIC Distributor interface general definitions
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******************************************************************************/
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/* Constants to categorise interrupts */
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#define MIN_SGI_ID U(0)
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#define MIN_SEC_SGI_ID U(8)
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#define MIN_PPI_ID U(16)
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#define MIN_SPI_ID U(32)
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#define MAX_SPI_ID U(1019)
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#define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + U(1))
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#define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID)
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/* Mask for the priority field common to all GIC interfaces */
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#define GIC_PRI_MASK U(0xff)
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/* Mask for the configuration field common to all GIC interfaces */
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#define GIC_CFG_MASK U(0x3)
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/* Constant to indicate a spurious interrupt in all GIC versions */
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#define GIC_SPURIOUS_INTERRUPT U(1023)
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/* Interrupt configurations: 2-bit fields with LSB reserved */
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#define GIC_INTR_CFG_LEVEL (0 << 1)
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#define GIC_INTR_CFG_EDGE (1 << 1)
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/* Highest possible interrupt priorities */
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#define GIC_HIGHEST_SEC_PRIORITY U(0x00)
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#define GIC_HIGHEST_NS_PRIORITY U(0x80)
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/*******************************************************************************
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* GIC Distributor interface register offsets that are common to GICv3 & GICv2
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******************************************************************************/
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#define GICD_CTLR U(0x0)
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#define GICD_TYPER U(0x4)
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#define GICD_IIDR U(0x8)
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#define GICD_IGROUPR U(0x80)
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#define GICD_ISENABLER U(0x100)
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#define GICD_ICENABLER U(0x180)
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#define GICD_ISPENDR U(0x200)
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#define GICD_ICPENDR U(0x280)
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#define GICD_ISACTIVER U(0x300)
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#define GICD_ICACTIVER U(0x380)
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#define GICD_IPRIORITYR U(0x400)
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#define GICD_ICFGR U(0xc00)
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#define GICD_NSACR U(0xe00)
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/* GICD_CTLR bit definitions */
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#define CTLR_ENABLE_G0_SHIFT 0
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#define CTLR_ENABLE_G0_MASK U(0x1)
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#define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT)
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/*******************************************************************************
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* GIC Distributor interface register constants that are common to GICv3 & GICv2
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******************************************************************************/
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#define PIDR2_ARCH_REV_SHIFT 4
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#define PIDR2_ARCH_REV_MASK U(0xf)
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/* GICv3 revision as reported by the PIDR2 register */
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#define ARCH_REV_GICV3 U(0x3)
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/* GICv2 revision as reported by the PIDR2 register */
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#define ARCH_REV_GICV2 U(0x2)
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/* GICv1 revision as reported by the PIDR2 register */
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#define ARCH_REV_GICV1 U(0x1)
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#define IGROUPR_SHIFT 5
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#define ISENABLER_SHIFT 5
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#define ICENABLER_SHIFT ISENABLER_SHIFT
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#define ISPENDR_SHIFT 5
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#define ICPENDR_SHIFT ISPENDR_SHIFT
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#define ISACTIVER_SHIFT 5
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#define ICACTIVER_SHIFT ISACTIVER_SHIFT
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#define IPRIORITYR_SHIFT 2
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#define ITARGETSR_SHIFT 2
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#define ICFGR_SHIFT 4
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#define NSACR_SHIFT 4
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/* GICD_TYPER shifts and masks */
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#define TYPER_IT_LINES_NO_SHIFT U(0)
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#define TYPER_IT_LINES_NO_MASK U(0x1f)
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/* Value used to initialize Normal world interrupt priorities four at a time */
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#define GICD_IPRIORITYR_DEF_VAL \
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(GIC_HIGHEST_NS_PRIORITY | \
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(GIC_HIGHEST_NS_PRIORITY << 8) | \
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(GIC_HIGHEST_NS_PRIORITY << 16) | \
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(GIC_HIGHEST_NS_PRIORITY << 24))
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#endif /* GIC_COMMON_H */
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