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https://github.com/ARM-software/arm-trusted-firmware.git
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de3d704d74
At the moment, various parts of the Trusted Firmware code assume that the granule size used is 4 KB. For example, the linker scripts enforce 4 KB alignment restrictions on some sections. However, the ARMv8-A architecture allows 16 KB and 64 KB granule sizes as well. Some other parts of the TF code, particularly the architectural code and definitions, have been implemented with this in mind and cater for all 3 cases. This discrepancy creates some confusion as to what is effectively supported in TF. This patch adds some code comments and clarification in the documentation to make this limitation clearer. Change-Id: I1f202369b240d8bed9d43d57ecd2a548c86c8598 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
121 lines
4.2 KiB
C
121 lines
4.2 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __XLAT_TABLES_DEFS_H__
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#define __XLAT_TABLES_DEFS_H__
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#include <utils_def.h>
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/* Miscellaneous MMU related constants */
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#define NUM_2MB_IN_GB (U(1) << 9)
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#define NUM_4K_IN_2MB (U(1) << 9)
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#define NUM_GB_IN_4GB (U(1) << 2)
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#define TWO_MB_SHIFT U(21)
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#define ONE_GB_SHIFT U(30)
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#define FOUR_KB_SHIFT U(12)
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#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
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#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
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#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
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#define INVALID_DESC U(0x0)
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#define BLOCK_DESC U(0x1) /* Table levels 0-2 */
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#define TABLE_DESC U(0x3) /* Table levels 0-2 */
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#define PAGE_DESC U(0x3) /* Table level 3 */
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#define DESC_MASK U(0x3)
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#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
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#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
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#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
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/* XN: Translation regimes that support one VA range (EL2 and EL3). */
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#define XN (ULL(1) << 2)
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/* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */
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#define UXN (ULL(1) << 2)
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#define PXN (ULL(1) << 1)
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#define CONT_HINT (ULL(1) << 0)
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#define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)
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#define NON_GLOBAL (U(1) << 9)
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#define ACCESS_FLAG (U(1) << 8)
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#define NSH (U(0x0) << 6)
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#define OSH (U(0x2) << 6)
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#define ISH (U(0x3) << 6)
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#define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)
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/*
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* The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or
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* 64KB. However, TF only supports the 4KB case at the moment.
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*/
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#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
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#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT)
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#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
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#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
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#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */
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#define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT)
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#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */
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#define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT)
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#define XLAT_TABLE_LEVEL_MAX U(3)
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/* Values for number of entries in each MMU translation table */
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#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
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#define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT)
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#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
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/* Values to convert a memory address to an index into a translation table */
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#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
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#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \
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((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
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#define XLAT_BLOCK_SIZE(level) ((u_register_t)1 << XLAT_ADDR_SHIFT(level))
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/* Mask to get the bits used to index inside a block of a certain level */
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#define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - 1)
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/* Mask to get the address bits common to a block of a certain table level*/
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#define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level))
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/*
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* AP[1] bit is ignored by hardware and is
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* treated as if it is One in EL2/EL3
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*/
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#define AP_RO (U(0x1) << 5)
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#define AP_RW (U(0x0) << 5)
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#define NS (U(0x1) << 3)
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#define ATTR_NON_CACHEABLE_INDEX U(0x2)
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#define ATTR_DEVICE_INDEX U(0x1)
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#define ATTR_IWBWA_OWBWA_NTR_INDEX U(0x0)
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#define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2)
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/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
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#define ATTR_NON_CACHEABLE U(0x44)
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/* Device-nGnRE */
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#define ATTR_DEVICE U(0x4)
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/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
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#define ATTR_IWBWA_OWBWA_NTR U(0xff)
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#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
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#define ATTR_INDEX_MASK U(0x3)
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#define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK)
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/*
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* Flags to override default values used to program system registers while
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* enabling the MMU.
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*/
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#define DISABLE_DCACHE (U(1) << 0)
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/*
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* This flag marks the translation tables are Non-cacheable for MMU accesses.
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* If the flag is not specified, by default the tables are cacheable.
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*/
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#define XLAT_TABLE_NC (U(1) << 1)
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#endif /* __XLAT_TABLES_DEFS_H__ */
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