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https://github.com/ARM-software/arm-trusted-firmware.git
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dd108c3c1f
Add the dram retention support for i.MX8MQ. As there is no enough ocram space available before entering TF-A, so the timing info need to be copied from dram into ocram. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Id8264c342fd62e297b1969cba5ed505450c78a25
136 lines
3.7 KiB
C
136 lines
3.7 KiB
C
/*
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* Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <dram.h>
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#include <gpc.h>
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#include <imx8m_psci.h>
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#include <plat_imx8.h>
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int imx_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
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int pwr_type = psci_get_pstate_type(power_state);
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int state_id = psci_get_pstate_id(power_state);
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if (pwr_lvl > PLAT_MAX_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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if (pwr_type == PSTATE_TYPE_STANDBY) {
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CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
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CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
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}
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if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) {
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CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE;
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CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE;
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}
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return PSCI_E_SUCCESS;
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}
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void imx_domain_suspend(const psci_power_state_t *target_state)
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{
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uint64_t base_addr = BL31_START;
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uint64_t mpidr = read_mpidr_el1();
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unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
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if (is_local_state_off(CORE_PWR_STATE(target_state))) {
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/* disable the cpu interface */
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plat_gic_cpuif_disable();
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imx_set_cpu_secure_entry(core_id, base_addr);
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imx_set_cpu_lpm(core_id, true);
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} else {
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dsb();
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write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
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isb();
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}
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if (is_local_state_off(CLUSTER_PWR_STATE(target_state)))
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imx_set_cluster_powerdown(core_id, true);
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else
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imx_set_cluster_standby(true);
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if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
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imx_set_sys_lpm(core_id, true);
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dram_enter_retention();
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}
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}
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void imx_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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uint64_t mpidr = read_mpidr_el1();
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unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr);
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/* check the system level status */
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if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) {
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dram_exit_retention();
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imx_set_sys_lpm(core_id, false);
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imx_clear_rbc_count();
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}
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/* check the cluster level power status */
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if (is_local_state_off(CLUSTER_PWR_STATE(target_state)))
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imx_set_cluster_powerdown(core_id, false);
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else
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imx_set_cluster_standby(false);
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/* check the core level power status */
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if (is_local_state_off(CORE_PWR_STATE(target_state))) {
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/* clear the core lpm setting */
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imx_set_cpu_lpm(core_id, false);
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/* enable the gic cpu interface */
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plat_gic_cpuif_enable();
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} else {
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write_scr_el3(read_scr_el3() & (~0x4));
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isb();
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}
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}
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void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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unsigned int i;
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for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE;
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}
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static const plat_psci_ops_t imx_plat_psci_ops = {
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.pwr_domain_on = imx_pwr_domain_on,
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.pwr_domain_on_finish = imx_pwr_domain_on_finish,
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.pwr_domain_off = imx_pwr_domain_off,
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.validate_ns_entrypoint = imx_validate_ns_entrypoint,
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.validate_power_state = imx_validate_power_state,
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.cpu_standby = imx_cpu_standby,
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.pwr_domain_suspend = imx_domain_suspend,
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.pwr_domain_suspend_finish = imx_domain_suspend_finish,
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.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
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.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
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.system_reset = imx_system_reset,
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.system_reset2 = imx_system_reset2,
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.system_off = imx_system_off,
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};
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/* export the platform specific psci ops */
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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imx_mailbox_init(sec_entrypoint);
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/* sec_entrypoint is used for warm reset */
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*psci_ops = &imx_plat_psci_ops;
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return 0;
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}
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