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c9512bca3b
Change-Id: I5993b425445ee794e6d2a792c244c0af53640655 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arm_config.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include <smmu_v3.h>
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#include "fvp_private.h"
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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/* Initialize the platform config for future decision making */
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fvp_config_setup();
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/*
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* Initialize the correct interconnect for this cluster during cold
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* boot. No need for locks as no other CPU is active.
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*/
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fvp_interconnect_init();
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/*
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* Enable coherency in interconnect for the primary CPU's cluster.
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* Earlier bootloader stages might already do this (e.g. Trusted
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* Firmware's BL1 does it) but we can't assume so. There is no harm in
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* executing this code twice anyway.
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* FVP PSCI code will enable coherency for other clusters.
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*/
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fvp_interconnect_enable();
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/* On FVP RevC, intialize SMMUv3 */
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if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
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smmuv3_init(PLAT_FVP_SMMUV3_BASE);
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}
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