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dc78e62d80
This patch adds two new compile time options to enable SME in TF-A: ENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and secure worlds respectively. Setting ENABLE_SME_FOR_NS=1 will enable SME for non-secure worlds and trap SME, SVE, and FPU/SIMD instructions in secure context. Setting ENABLE_SME_FOR_SWD=1 will disable these traps, but support for SME context management does not yet exist in SPM so building with SPD=spmd will fail. The existing ENABLE_SVE_FOR_NS and ENABLE_SVE_FOR_SWD options cannot be used with SME as it is a superset of SVE and will enable SVE and FPU/SIMD along with SME. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iaaac9d22fe37b4a92315207891da848a8fd0ed73
27 lines
767 B
C
27 lines
767 B
C
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SME_H
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#define SME_H
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#include <stdbool.h>
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#include <context.h>
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/*
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* Maximum value of LEN field in SMCR_ELx. This is different than the maximum
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* supported value which is platform dependent. In the first version of SME the
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* LEN field is limited to 4 bits but will be expanded in future iterations.
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* To support different versions, the code that discovers the supported vector
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* lengths will write the max value into SMCR_ELx then read it back to see how
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* many bits are implemented.
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*/
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#define SME_SMCR_LEN_MAX U(0x1FF)
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void sme_enable(cpu_context_t *context);
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void sme_disable(cpu_context_t *context);
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#endif /* SME_H */
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