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da04341ed5
Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
207 lines
6 KiB
C
207 lines
6 KiB
C
/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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/* CPU topology */
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#define PLAT_MAX_CORES_PER_CLUSTER U(2)
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#define PLAT_CLUSTER_COUNT U(12)
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#define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \
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PLAT_MAX_CORES_PER_CLUSTER)
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/* Macros to read the SQ power domain state */
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#define SQ_PWR_LVL0 MPIDR_AFFLVL0
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#define SQ_PWR_LVL1 MPIDR_AFFLVL1
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#define SQ_PWR_LVL2 MPIDR_AFFLVL2
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#define SQ_CORE_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL0]
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#define SQ_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[SQ_PWR_LVL1]
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#define SQ_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > SQ_PWR_LVL1) ?\
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(state)->pwr_domain_state[SQ_PWR_LVL2] : 0)
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#define PLAT_MAX_PWR_LVL U(1)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define SQ_LOCAL_STATE_RUN 0
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#define SQ_LOCAL_STATE_RET 1
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#define SQ_LOCAL_STATE_OFF 2
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES 8
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#define MAX_MMAP_REGIONS 8
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#if TRUSTED_BOARD_BOOT
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#define PLATFORM_STACK_SIZE 0x1000
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#else
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#define PLATFORM_STACK_SIZE 0x400
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#endif
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#if !RESET_TO_BL31
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/* A mailbox page will be mapped from BL2 and BL31 */
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#define BL2_MAILBOX_BASE 0x0403f000
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#define BL2_MAILBOX_SIZE 0x1000
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#define PLAT_SQ_BOOTIDX_BASE 0x08510000
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#define PLAT_SQ_MAX_BOOT_INDEX 2
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#define MAX_IO_HANDLES 2
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#define MAX_IO_DEVICES 2
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#define MAX_IO_BLOCK_DEVICES U(1)
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#define BL2_BASE 0x04000000
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#define BL2_SIZE (256 * 1024)
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#define BL2_LIMIT (BL2_BASE + BL2_SIZE)
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/* If BL2 is enabled, the BL31 is loaded on secure DRAM */
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#define BL31_BASE 0xfbe00000
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#define BL31_SIZE 0x00100000
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#else
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#define BL31_BASE 0x04000000
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#define BL31_SIZE 0x00080000
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#endif
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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#define BL32_BASE 0xfc000000
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#define BL32_SIZE 0x03c00000
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#define BL32_LIMIT (BL32_BASE + BL32_SIZE)
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/* Alternative BL33 */
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#define PLAT_SQ_BL33_BASE 0xe0000000
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#define PLAT_SQ_BL33_SIZE 0x00200000
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/* FWU FIP IO base */
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#define PLAT_SQ_FIP_IOBASE 0x08600000
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#define PLAT_SQ_FIP_MAXSIZE 0x00400000
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#define PLAT_SQ_CCN_BASE 0x32000000
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#define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \
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0, /* Cluster 0 */ \
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18, /* Cluster 1 */ \
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11, /* Cluster 2 */ \
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29, /* Cluster 3 */ \
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35, /* Cluster 4 */ \
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17, /* Cluster 5 */ \
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12, /* Cluster 6 */ \
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30, /* Cluster 7 */ \
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14, /* Cluster 8 */ \
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32, /* Cluster 9 */ \
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15, /* Cluster 10 */ \
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33 /* Cluster 11 */
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/* UART related constants */
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#define PLAT_SQ_BOOT_UART_BASE 0x2A400000
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#define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000
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#define SQ_CONSOLE_BAUDRATE 115200
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#define SQ_SYS_CNTCTL_BASE 0x2a430000
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#define SQ_SYS_TIMCTL_BASE 0x2a810000
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#define PLAT_SQ_NSTIMER_FRAME_ID 0
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#define SQ_SYS_CNT_BASE_NS 0x2a830000
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#define DRAMINFO_BASE 0x2E00FFC0
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#define PLAT_SQ_MHU_BASE 0x45000000
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#define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000
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#define SCPI_CMD_GET_DRAMINFO 0x1
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#define SQ_BOOT_CFG_ADDR 0x45410000
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#define PLAT_SQ_PRIMARY_CPU_SHIFT 8
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#define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6
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#define PLAT_SQ_GICD_BASE 0x30000000
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#define PLAT_SQ_GICR_BASE 0x30400000
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#define PLAT_SQ_GPIO_BASE 0x51000000
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#define PLAT_SPM_BUF_BASE (BL32_LIMIT - 32 * PLAT_SPM_BUF_SIZE)
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#define PLAT_SPM_BUF_SIZE ULL(0x10000)
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#define PLAT_SPM_SPM_BUF_EL0_MMAP MAP_REGION2(PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_SIZE, \
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MT_RO_DATA | MT_SECURE | \
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MT_USER, PAGE_SIZE)
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#define PLAT_SP_IMAGE_NS_BUF_BASE BL32_LIMIT
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#define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x200000)
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#define PLAT_SP_IMAGE_NS_BUF_MMAP MAP_REGION2(PLAT_SP_IMAGE_NS_BUF_BASE, \
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PLAT_SP_IMAGE_NS_BUF_BASE, \
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PLAT_SP_IMAGE_NS_BUF_SIZE, \
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MT_RW_DATA | MT_NS | \
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MT_USER, PAGE_SIZE)
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#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x10000)
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#define PLAT_SP_IMAGE_STACK_SIZE (32 * PLAT_SP_IMAGE_STACK_PCPU_SIZE)
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#define PLAT_SP_IMAGE_STACK_BASE (PLAT_SQ_SP_HEAP_BASE + PLAT_SQ_SP_HEAP_SIZE)
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#define PLAT_SQ_SP_IMAGE_SIZE ULL(0x200000)
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#define PLAT_SQ_SP_IMAGE_MMAP MAP_REGION2(BL32_BASE, BL32_BASE, \
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PLAT_SQ_SP_IMAGE_SIZE, \
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MT_CODE | MT_SECURE | \
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MT_USER, PAGE_SIZE)
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#define PLAT_SQ_SP_HEAP_BASE (BL32_BASE + PLAT_SQ_SP_IMAGE_SIZE)
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#define PLAT_SQ_SP_HEAP_SIZE ULL(0x800000)
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#define PLAT_SQ_SP_IMAGE_RW_MMAP MAP_REGION2(PLAT_SQ_SP_HEAP_BASE, \
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PLAT_SQ_SP_HEAP_BASE, \
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(PLAT_SQ_SP_HEAP_SIZE + \
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PLAT_SP_IMAGE_STACK_SIZE), \
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MT_RW_DATA | MT_SECURE | \
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MT_USER, PAGE_SIZE)
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#define PLAT_SQ_SP_PRIV_BASE (PLAT_SP_IMAGE_STACK_BASE + \
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PLAT_SP_IMAGE_STACK_SIZE)
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#define PLAT_SQ_SP_PRIV_SIZE ULL(0x40000)
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#define PLAT_SP_PRI 0x20
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#define PLAT_PRI_BITS 2
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#define PLAT_SPM_COOKIE_0 ULL(0)
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#define PLAT_SPM_COOKIE_1 ULL(0)
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/* Total number of memory regions with distinct properties */
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#define PLAT_SP_IMAGE_NUM_MEM_REGIONS 6
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#define PLAT_SP_IMAGE_MMAP_REGIONS 30
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#define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME ".sp_xlat_table"
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#define PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME ".sp_xlat_table"
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#define PLAT_SQ_UART1_BASE PLAT_SQ_BOOT_UART_BASE
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#define PLAT_SQ_UART1_SIZE ULL(0x1000)
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#define PLAT_SQ_UART1_MMAP MAP_REGION_FLAT(PLAT_SQ_UART1_BASE, \
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PLAT_SQ_UART1_SIZE, \
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MT_DEVICE | MT_RW | \
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MT_NS | MT_PRIVILEGED)
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#define PLAT_SQ_PERIPH_BASE 0x50000000
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#define PLAT_SQ_PERIPH_SIZE ULL(0x8000000)
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#define PLAT_SQ_PERIPH_MMAP MAP_REGION_FLAT(PLAT_SQ_PERIPH_BASE, \
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PLAT_SQ_PERIPH_SIZE, \
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MT_DEVICE | MT_RW | \
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MT_NS | MT_USER)
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#define PLAT_SQ_FLASH_BASE 0x08000000
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#define PLAT_SQ_FLASH_SIZE ULL(0x8000000)
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#define PLAT_SQ_FLASH_MMAP MAP_REGION_FLAT(PLAT_SQ_FLASH_BASE, \
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PLAT_SQ_FLASH_SIZE, \
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MT_DEVICE | MT_RW | \
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MT_NS | MT_USER)
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#endif /* PLATFORM_DEF_H */
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