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da04341ed5
Some of our specialized sections are not prefixed with the conventional period. The compiler uses input section names to derive certain other section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be difficult to select in linker scripts when there is a lack of a delimiter. This change introduces the period prefix to all specialized section names. BREAKING-CHANGE: All input and output linker section names have been prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`. Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c Signed-off-by: Chris Kay <chris.kay@arm.com>
271 lines
7.9 KiB
C
271 lines
7.9 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/interrupt_props.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/gic_common.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include "rcar_def.h"
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#include "rcar_private.h"
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#include "rcar_version.h"
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#if (IMAGE_BL2)
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extern void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *p);
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extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
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#endif
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const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
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__attribute__ ((__section__(".ro"))) = VERSION_OF_RENESAS;
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#define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \
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RCAR_SHARED_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
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FLASH0_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
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DRAM1_NS_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
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DEVICE_RCAR_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DEVICE_RCAR2 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, \
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DEVICE_RCAR_SIZE2, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_SRAM MAP_REGION_FLAT(DEVICE_SRAM_BASE, \
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DEVICE_SRAM_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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#define MAP_SRAM_STACK MAP_REGION_FLAT(DEVICE_SRAM_STACK_BASE, \
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DEVICE_SRAM_STACK_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_ATFW_CRASH MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, \
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RCAR_BL31_CRASH_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_ATFW_LOG MAP_REGION_FLAT(RCAR_BL31_LOG_BASE, \
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RCAR_BL31_LOG_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#if IMAGE_BL2
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#define MAP_DRAM0 MAP_REGION_FLAT(DRAM1_BASE, \
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DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_REG0 MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
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DEVICE_RCAR_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_RAM0 MAP_REGION_FLAT(RCAR_SYSRAM_BASE, \
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RCAR_SYSRAM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_REG1 MAP_REGION_FLAT(REG1_BASE, \
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REG1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_ROM MAP_REGION_FLAT(ROM0_BASE, \
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ROM0_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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#define MAP_REG2 MAP_REGION_FLAT(REG2_BASE, \
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REG2_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DRAM1 MAP_REGION_FLAT(DRAM_40BIT_BASE, \
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DRAM_40BIT_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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#ifdef BL32_BASE
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#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_BASE, \
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BL32_LIMIT - BL32_BASE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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#if IMAGE_BL2
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static const mmap_region_t rcar_mmap[] = {
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MAP_FLASH0, /* 0x08000000 - 0x0BFFFFFF RPC area */
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MAP_DRAM0, /* 0x40000000 - 0xBFFFFFFF DRAM area(Legacy) */
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MAP_REG0, /* 0xE6000000 - 0xE62FFFFF SoC register area */
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MAP_RAM0, /* 0xE6300000 - 0xE6303FFF System RAM area */
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MAP_REG1, /* 0xE6400000 - 0xEAFFFFFF SoC register area */
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MAP_ROM, /* 0xEB100000 - 0xEB127FFF boot ROM area */
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MAP_REG2, /* 0xEC000000 - 0xFFFFFFFF SoC register area */
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MAP_DRAM1, /* 0x0400000000 - 0x07FFFFFFFF DRAM area(4GB over) */
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{0}
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};
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#endif
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#if IMAGE_BL31
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static const mmap_region_t rcar_mmap[] = {
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MAP_SHARED_RAM,
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MAP_ATFW_CRASH,
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MAP_ATFW_LOG,
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MAP_DEVICE_RCAR,
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MAP_DEVICE_RCAR2,
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MAP_SRAM,
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MAP_SRAM_STACK,
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{0}
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};
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#endif
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#if IMAGE_BL32
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static const mmap_region_t rcar_mmap[] = {
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MAP_DEVICE0,
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MAP_DEVICE1,
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{0}
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};
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#endif
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CASSERT(ARRAY_SIZE(rcar_mmap) + RCAR_BL_REGIONS
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<= MAX_MMAP_REGIONS, assert_max_mmap_regions);
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/*
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* Macro generating the code for the function setting up the pagetables as per
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* the platform memory map & initialize the mmu, for the given exception level
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*/
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#if USE_COHERENT_MEM
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void rcar_configure_mmu_el3(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit,
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unsigned long coh_start,
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unsigned long coh_limit)
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{
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mmap_add_region(total_base, total_base, total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
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MT_MEMORY | MT_RO | MT_SECURE);
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mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
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MT_DEVICE | MT_RW | MT_SECURE);
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mmap_add(rcar_mmap);
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init_xlat_tables();
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enable_mmu_el3(0);
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}
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#else
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void rcar_configure_mmu_el3(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start,
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unsigned long ro_limit)
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{
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mmap_add_region(total_base, total_base, total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
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MT_MEMORY | MT_RO | MT_SECURE);
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mmap_add(rcar_mmap);
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init_xlat_tables();
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enable_mmu_el3(0);
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}
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#endif
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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#if (IMAGE_BL2)
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uint32_t cert, len;
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uintptr_t dst;
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int32_t ret;
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ret = rcar_get_certificate(NON_TRUSTED_FW_CONTENT_CERT_ID, &cert);
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if (ret) {
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ERROR("%s : cert file load error", __func__);
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return NS_IMAGE_OFFSET;
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}
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rcar_read_certificate((uint64_t) cert, &len, &dst);
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return dst;
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#else
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return NS_IMAGE_OFFSET;
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#endif
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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unsigned int freq;
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freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
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if (freq == 0)
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panic();
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return freq;
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}
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void plat_rcar_gic_init(void)
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{
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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}
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static const interrupt_prop_t interrupt_props[] = {
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#if IMAGE_BL2
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INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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#else
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
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INTR_PROP_DESC(ARM_IRQ_SEC_RPC, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(ARM_IRQ_SEC_TIMER, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(ARM_IRQ_SEC_TIMER_UP, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(ARM_IRQ_SEC_WDT, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_SecPKA, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(ARM_IRQ_SEC_CRYPT_PubPKA, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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#endif
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};
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static const gicv2_driver_data_t plat_gicv2_driver_data = {
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.interrupt_props = interrupt_props,
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.interrupt_props_num = (uint32_t) ARRAY_SIZE(interrupt_props),
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.gicd_base = RCAR_GICD_BASE,
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.gicc_base = RCAR_GICC_BASE,
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};
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void plat_rcar_gic_driver_init(void)
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{
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gicv2_driver_init(&plat_gicv2_driver_data);
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}
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