mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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d8e919c7b8
Initial commit for Socionext UniPhier SoC support. BL1, Bl2, and BL31 are supported. Refer to docs/plat/socionext-uniphier.md for more detais. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
59 lines
1.7 KiB
C
59 lines
1.7 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <platform_def.h>
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#include <xlat_tables_v2.h>
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#define UNIPHIER_OCM_REGION_BASE 0x30000000
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#define UNIPHIER_OCM_REGION_SIZE 0x00040000
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#define UNIPHIER_REG_REGION_BASE 0x50000000
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#define UNIPHIER_REG_REGION_SIZE 0x20000000
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void uniphier_mmap_setup(uintptr_t total_base, size_t total_size,
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const struct mmap_region *mmap)
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{
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VERBOSE("Trusted RAM seen by this BL image: %p - %p\n",
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(void *)total_base, (void *)(total_base + total_size));
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mmap_add_region(total_base, total_base,
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total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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/* remap the code section */
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VERBOSE("Code region: %p - %p\n",
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(void *)BL_CODE_BASE, (void *)BL_CODE_END);
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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round_up(BL_CODE_END, PAGE_SIZE) - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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/* remap the coherent memory region */
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VERBOSE("Coherent region: %p - %p\n",
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(void *)BL_COHERENT_RAM_BASE, (void *)BL_COHERENT_RAM_END);
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mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE);
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/*
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* on-chip SRAM region: should be DEVICE attribute because the USB
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* load functions provided by the ROM use this memory region as a work
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* area, but do not cater to cache coherency.
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*/
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mmap_add_region(UNIPHIER_OCM_REGION_BASE, UNIPHIER_OCM_REGION_BASE,
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UNIPHIER_OCM_REGION_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE);
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/* register region */
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mmap_add_region(UNIPHIER_REG_REGION_BASE, UNIPHIER_REG_REGION_BASE,
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UNIPHIER_REG_REGION_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE);
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/* additional regions if needed */
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if (mmap)
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mmap_add(mmap);
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init_xlat_tables();
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}
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