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https://github.com/ARM-software/arm-trusted-firmware.git
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d8e919c7b8
Initial commit for Socionext UniPhier SoC support. BL1, Bl2, and BL31 are supported. Refer to docs/plat/socionext-uniphier.md for more detais. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
99 lines
2.5 KiB
C
99 lines
2.5 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <gicv3.h>
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#include <platform.h>
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#include <platform_def.h>
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#include "uniphier.h"
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static uintptr_t uniphier_rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static const unsigned int g0_interrupt_array[] = {
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8, /* SGI0 */
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14, /* SGI6 */
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};
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static const unsigned int g1s_interrupt_array[] = {
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29, /* Timer */
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9, /* SGI1 */
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10, /* SGI2 */
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11, /* SGI3 */
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12, /* SGI4 */
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13, /* SGI5 */
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15, /* SGI7 */
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};
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static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr)
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{
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return plat_core_pos_by_mpidr(mpidr);
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}
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static const struct gicv3_driver_data uniphier_gic_driver_data[] = {
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[UNIPHIER_SOC_LD11] = {
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.gicd_base = 0x5fe00000,
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.gicr_base = 0x5fe40000,
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.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
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.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
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.g0_interrupt_array = g0_interrupt_array,
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.g1s_interrupt_array = g1s_interrupt_array,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = uniphier_rdistif_base_addrs,
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.mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
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},
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[UNIPHIER_SOC_LD20] = {
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.gicd_base = 0x5fe00000,
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.gicr_base = 0x5fe80000,
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.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
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.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
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.g0_interrupt_array = g0_interrupt_array,
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.g1s_interrupt_array = g1s_interrupt_array,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = uniphier_rdistif_base_addrs,
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.mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
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},
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[UNIPHIER_SOC_PXS3] = {
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.gicd_base = 0x5fe00000,
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.gicr_base = 0x5fe80000,
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.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
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.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
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.g0_interrupt_array = g0_interrupt_array,
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.g1s_interrupt_array = g1s_interrupt_array,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = uniphier_rdistif_base_addrs,
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.mpidr_to_core_pos = uniphier_mpidr_to_core_pos,
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},
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};
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void uniphier_gic_driver_init(unsigned int soc)
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{
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assert(soc < ARRAY_SIZE(uniphier_gic_driver_data));
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gicv3_driver_init(&uniphier_gic_driver_data[soc]);
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}
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void uniphier_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void uniphier_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void uniphier_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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void uniphier_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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