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d801a1d035
The translation tables allocated for the Secure Partition do not need
to be treated as a special case. They can be put amongst the other
tables mapping BL31's general purpose memory. They will be mapped with
the same attributes as them, which is fine.
The explicit alignment constraint in BL31's linker script to pad the
last page of memory allocated to the Secure Partition's translation
tables is useless too, as page tables are per se pages, thus their
end address is naturally aligned on a page-boundary.
In fact, this patch does not change the existing behaviour. Since
patch 22282bb68a ("SPM: Move all SP-related info to SP context
struct"), the secure_partition.c file has been renamed into sp_xlat.c
but the linker script has not been properly updated. As a result, the
SP translation tables are not specifically put at the start of the
xlat_table linker section, the __SP_IMAGE_XLAT_TABLES_START__/_END__
symbols have the same value, the size of the resulting mmap_region
covering these xlat tables is 0 and so it is ignored.
Change-Id: I4cf0a4cc090298811cca53fc9cee74df0f2b1512
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
268 lines
7.8 KiB
ArmAsm
268 lines
7.8 KiB
ArmAsm
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <xlat_tables_defs.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl31_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
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}
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#ifdef PLAT_EXTRA_LD_SCRIPT
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#include <plat.ld.S>
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#endif
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SECTIONS
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{
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. = BL31_BASE;
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ASSERT(. == ALIGN(PAGE_SIZE),
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"BL31_BASE address is not aligned on a page boundary.")
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#if SEPARATE_CODE_AND_RODATA
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.text . : {
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__TEXT_START__ = .;
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*bl31_entrypoint.o(.text*)
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*(.text*)
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*(.vectors)
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. = NEXT(PAGE_SIZE);
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__TEXT_END__ = .;
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} >RAM
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.rodata . : {
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__RODATA_START__ = .;
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*(.rodata*)
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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. = ALIGN(8);
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__RT_SVC_DESCS_START__ = .;
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KEEP(*(rt_svc_descs))
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__RT_SVC_DESCS_END__ = .;
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#if ENABLE_PMF
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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. = ALIGN(8);
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__PMF_SVC_DESCS_START__ = .;
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KEEP(*(pmf_svc_descs))
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__PMF_SVC_DESCS_END__ = .;
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#endif /* ENABLE_PMF */
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/*
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* Ensure 8-byte alignment for cpu_ops so that its fields are also
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* aligned. Also ensure cpu_ops inclusion.
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*/
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. = ALIGN(8);
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__CPU_OPS_START__ = .;
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KEEP(*(cpu_ops))
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__CPU_OPS_END__ = .;
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/* Place pubsub sections for events */
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. = ALIGN(8);
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#include <pubsub_events.h>
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. = NEXT(PAGE_SIZE);
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__RODATA_END__ = .;
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} >RAM
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#else
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ro . : {
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__RO_START__ = .;
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*bl31_entrypoint.o(.text*)
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*(.text*)
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*(.rodata*)
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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. = ALIGN(8);
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__RT_SVC_DESCS_START__ = .;
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KEEP(*(rt_svc_descs))
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__RT_SVC_DESCS_END__ = .;
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#if ENABLE_PMF
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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. = ALIGN(8);
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__PMF_SVC_DESCS_START__ = .;
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KEEP(*(pmf_svc_descs))
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__PMF_SVC_DESCS_END__ = .;
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#endif /* ENABLE_PMF */
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/*
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* Ensure 8-byte alignment for cpu_ops so that its fields are also
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* aligned. Also ensure cpu_ops inclusion.
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*/
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. = ALIGN(8);
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__CPU_OPS_START__ = .;
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KEEP(*(cpu_ops))
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__CPU_OPS_END__ = .;
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/* Place pubsub sections for events */
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. = ALIGN(8);
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#include <pubsub_events.h>
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*(.vectors)
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__RO_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as read-only,
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* executable. No RW data from the next section must creep in.
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* Ensure the rest of the current memory page is unused.
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*/
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. = NEXT(PAGE_SIZE);
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__RO_END__ = .;
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} >RAM
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#endif
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ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
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"cpu_ops not defined for this platform.")
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#if ENABLE_SPM
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/*
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* Exception vectors of the SPM shim layer. They must be aligned to a 2K
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* address, but we need to place them in a separate page so that we can set
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* individual permissions to them, so the actual alignment needed is 4K.
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*
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* There's no need to include this into the RO section of BL31 because it
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* doesn't need to be accessed by BL31.
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*/
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spm_shim_exceptions : ALIGN(PAGE_SIZE) {
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__SPM_SHIM_EXCEPTIONS_START__ = .;
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*(.spm_shim_exceptions)
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. = NEXT(PAGE_SIZE);
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__SPM_SHIM_EXCEPTIONS_END__ = .;
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} >RAM
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#endif
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/*
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* Define a linker symbol to mark start of the RW memory area for this
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* image.
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*/
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__RW_START__ = . ;
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/*
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* .data must be placed at a lower address than the stacks if the stack
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* protector is enabled. Alternatively, the .data.stack_protector_canary
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* section can be placed independently of the main .data section.
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*/
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.data . : {
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__DATA_START__ = .;
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*(.data*)
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__DATA_END__ = .;
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} >RAM
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#ifdef BL31_PROGBITS_LIMIT
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ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.")
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#endif
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stacks (NOLOAD) : {
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__STACKS_START__ = .;
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*(tzfw_normal_stacks)
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__STACKS_END__ = .;
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} >RAM
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/*
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* The .bss section gets initialised to 0 at runtime.
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* Its base address should be 16-byte aligned for better performance of the
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* zero-initialization code.
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*/
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.bss (NOLOAD) : ALIGN(16) {
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__BSS_START__ = .;
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*(.bss*)
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*(COMMON)
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#if !USE_COHERENT_MEM
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/*
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* Bakery locks are stored in normal .bss memory
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*
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* Each lock's data is spread across multiple cache lines, one per CPU,
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* but multiple locks can share the same cache line.
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* The compiler will allocate enough memory for one CPU's bakery locks,
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* the remaining cache lines are allocated by the linker script
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*/
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. = ALIGN(CACHE_WRITEBACK_GRANULE);
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__BAKERY_LOCK_START__ = .;
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*(bakery_lock)
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. = ALIGN(CACHE_WRITEBACK_GRANULE);
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__PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
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. = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
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__BAKERY_LOCK_END__ = .;
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#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
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ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
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"PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
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#endif
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#endif
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#if ENABLE_PMF
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/*
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* Time-stamps are stored in normal .bss memory
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*
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* The compiler will allocate enough memory for one CPU's time-stamps,
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* the remaining memory for other CPU's is allocated by the
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* linker script
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*/
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. = ALIGN(CACHE_WRITEBACK_GRANULE);
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__PMF_TIMESTAMP_START__ = .;
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KEEP(*(pmf_timestamp_array))
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. = ALIGN(CACHE_WRITEBACK_GRANULE);
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__PMF_PERCPU_TIMESTAMP_END__ = .;
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__PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__);
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. = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1));
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__PMF_TIMESTAMP_END__ = .;
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#endif /* ENABLE_PMF */
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__BSS_END__ = .;
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} >RAM
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/*
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* The xlat_table section is for full, aligned page tables (4K).
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* Removing them from .bss avoids forcing 4K alignment on
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* the .bss section. The tables are initialized to zero by the translation
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* tables library.
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*/
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xlat_table (NOLOAD) : {
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*(xlat_table)
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} >RAM
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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* are not mixed with normal data. This is required to set up the correct
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* memory attributes for the coherent data page tables.
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*/
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coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
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__COHERENT_RAM_START__ = .;
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/*
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* Bakery locks are stored in coherent memory
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*
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* Each lock's data is contiguous and fully allocated by the compiler
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*/
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*(bakery_lock)
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*(tzfw_coherent_mem)
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__COHERENT_RAM_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked
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* as device memory. No other unexpected data must creep in.
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* Ensure the rest of the current memory page is unused.
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*/
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. = NEXT(PAGE_SIZE);
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__COHERENT_RAM_END__ = .;
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} >RAM
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#endif
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/*
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* Define a linker symbol to mark end of the RW memory area for this
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* image.
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*/
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__RW_END__ = .;
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__BL31_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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#if USE_COHERENT_MEM
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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#endif
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ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
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}
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