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d596023bff
Disabling AXI port, enabling host interface and both enabling/disabling software self-refresh services are already present inside the driver source code. Factorize by gathering them as services inside the generic part, and adapt driver to call these new functions. Add services to manage quasi-dynamic registers. DDRCTRL contains quasi-dynamic registers, which are dynamic only under some conditions defined by the user guide (with 4 groups). In our driver, out of reset state, only groups 3 and 4 are updated. Group 4 needs only sw_done/sw_done_ack sequence, already available. Group 3 sequence include more conditions, that are gathered in specific services. stm32mp_ddr_disable_host_interface() has been added to do this. Add dedicated generic service to toggle rfshctl3.refresh_update_level and wait for completion. Manage AXI ports and HIF when updating QD3 registers. Quasi-dynamic group 3 (QD3) registers are updated when DDR is not completely initialized, i.e. when AXI ports are not enabled and possibly when host interface (HIF) is not enabled too. In that case, a specific mechanism is necessary to restore the same conditions as before accessing QD3 registers. Static functions have been added to get AXI ports and HIF states and are used to determine the needed conditions to set/unset. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: I880f88b1cb6fc76199ad9ea33e9d63a5c469aed4
81 lines
2.1 KiB
C
81 lines
2.1 KiB
C
/*
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* Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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*/
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#ifndef STM32MP_DDR_H
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#define STM32MP_DDR_H
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#include <platform_def.h>
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enum stm32mp_ddr_base_type {
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DDR_BASE,
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DDRPHY_BASE,
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NONE_BASE
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};
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enum stm32mp_ddr_reg_type {
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REG_REG,
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REG_TIMING,
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REG_PERF,
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REG_MAP,
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REGPHY_REG,
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REGPHY_TIMING,
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REG_TYPE_NB
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};
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struct stm32mp_ddr_reg_desc {
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uint16_t offset; /* Offset for base address */
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uint8_t par_offset; /* Offset for parameter array */
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};
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struct stm32mp_ddr_reg_info {
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const char *name;
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const struct stm32mp_ddr_reg_desc *desc;
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uint8_t size;
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enum stm32mp_ddr_base_type base;
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};
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struct stm32mp_ddr_size {
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uint64_t base;
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uint64_t size;
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};
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struct stm32mp_ddr_priv {
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struct stm32mp_ddr_size info;
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struct stm32mp_ddrctl *ctl;
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struct stm32mp_ddrphy *phy;
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uintptr_t pwr;
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uintptr_t rcc;
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};
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struct stm32mp_ddr_info {
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const char *name;
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uint32_t speed; /* in kHz */
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size_t size; /* Memory size in byte = col * row * width */
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};
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#define DDR_DELAY_1US 1U
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#define DDR_DELAY_2US 2U
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#define DDR_DELAY_10US 10U
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#define DDR_DELAY_50US 50U
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#define DDR_TIMEOUT_500US 500U
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#define DDR_TIMEOUT_US_1S 1000000U
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void stm32mp_ddr_set_reg(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_reg_type type,
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const void *param, const struct stm32mp_ddr_reg_info *ddr_registers);
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void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl);
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int stm32mp_ddr_disable_axi_port(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_enable_host_interface(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_disable_host_interface(struct stm32mp_ddrctl *ctl);
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int stm32mp_ddr_sw_selfref_entry(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_sw_selfref_exit(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_set_qd3_update_conditions(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_unset_qd3_update_conditions(struct stm32mp_ddrctl *ctl);
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void stm32mp_ddr_wait_refresh_update_done_ack(struct stm32mp_ddrctl *ctl);
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int stm32mp_board_ddr_power_init(enum ddr_type ddr_type);
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#endif /* STM32MP_DDR_H */
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