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https://github.com/ARM-software/arm-trusted-firmware.git
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d50ece03d9
The files affected by this patch don't really depend on `xlat_tables.h`. By changing the included file it becomes easier to switch between the two versions of the translation tables library. Change-Id: Idae9171c490e0865cb55883b19eaf942457c4ccc Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
284 lines
8.7 KiB
ArmAsm
284 lines
8.7 KiB
ArmAsm
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <context.h>
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#include <el3_common_macros.S>
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#include <runtime_svc.h>
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#include <smcc_helpers.h>
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#include <smcc_macros.S>
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#include <xlat_tables_defs.h>
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.globl sp_min_vector_table
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.globl sp_min_entrypoint
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.globl sp_min_warm_entrypoint
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vector_base sp_min_vector_table
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b sp_min_entrypoint
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b plat_panic_handler /* Undef */
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b handle_smc /* Syscall */
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b plat_panic_handler /* Prefetch abort */
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b plat_panic_handler /* Data abort */
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b plat_panic_handler /* Reserved */
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b plat_panic_handler /* IRQ */
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b plat_panic_handler /* FIQ */
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/*
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* The Cold boot/Reset entrypoint for SP_MIN
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*/
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func sp_min_entrypoint
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#if !RESET_TO_SP_MIN
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/* ---------------------------------------------------------------
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* Preceding bootloader has populated r0 with a pointer to a
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* 'bl_params_t' structure & r1 with a pointer to platform
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* specific structure
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* ---------------------------------------------------------------
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*/
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mov r11, r0
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mov r12, r1
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/* ---------------------------------------------------------------------
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* For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
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* sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
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* and primary/secondary CPU logic should not be executed in this case.
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*
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* Also, assume that the previous bootloader has already set up the CPU
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* endianness and has initialised the memory.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_set_endian=0 \
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_warm_boot_mailbox=0 \
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_secondary_cold_boot=0 \
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_init_memory=0 \
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_init_c_runtime=1 \
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_exception_vectors=sp_min_vector_table
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/* ---------------------------------------------------------------------
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* Relay the previous bootloader's arguments to the platform layer
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* ---------------------------------------------------------------------
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*/
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mov r0, r11
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mov r1, r12
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#else
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/* ---------------------------------------------------------------------
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* For RESET_TO_SP_MIN systems which have a programmable reset address,
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* sp_min_entrypoint() is executed only on the cold boot path so we can
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* skip the warm boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_set_endian=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=sp_min_vector_table
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/* ---------------------------------------------------------------------
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* For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
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* to run so there's no argument to relay from a previous bootloader.
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* Zero the arguments passed to the platform layer to reflect that.
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* ---------------------------------------------------------------------
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*/
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mov r0, #0
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mov r1, #0
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#endif /* RESET_TO_SP_MIN */
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bl sp_min_early_platform_setup
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bl sp_min_plat_arch_setup
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/* Jump to the main function */
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bl sp_min_main
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/* -------------------------------------------------------------
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* Clean the .data & .bss sections to main memory. This ensures
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* that any global data which was initialised by the primary CPU
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* is visible to secondary CPUs before they enable their data
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* caches and participate in coherency.
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* -------------------------------------------------------------
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*/
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ldr r0, =__DATA_START__
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ldr r1, =__DATA_END__
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sub r1, r1, r0
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bl clean_dcache_range
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ldr r0, =__BSS_START__
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ldr r1, =__BSS_END__
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sub r1, r1, r0
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bl clean_dcache_range
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/* Program the registers in cpu_context and exit monitor mode */
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mov r0, #NON_SECURE
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bl cm_get_context
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/* Restore the SCR */
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ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR]
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stcopr r2, SCR
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isb
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/* Restore the SCTLR */
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ldr r2, [r0, #CTX_REGS_OFFSET + CTX_NS_SCTLR]
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stcopr r2, SCTLR
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bl smc_get_next_ctx
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/* The other cpu_context registers have been copied to smc context */
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b sp_min_exit
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endfunc sp_min_entrypoint
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/*
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* SMC handling function for SP_MIN.
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*/
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func handle_smc
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smcc_save_gp_mode_regs
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/* r0 points to smc_context */
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mov r2, r0 /* handle */
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ldcopr r0, SCR
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/*
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* Save SCR in stack. r1 is pushed to meet the 8 byte
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* stack alignment requirement.
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*/
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push {r0, r1}
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and r3, r0, #SCR_NS_BIT /* flags */
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/* Switch to Secure Mode*/
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bic r0, #SCR_NS_BIT
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stcopr r0, SCR
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isb
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ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */
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/* Check whether an SMC64 is issued */
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tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT)
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beq 1f /* SMC32 is detected */
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mov r0, #SMC_UNK
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str r0, [r2, #SMC_CTX_GPREG_R0]
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mov r0, r2
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b 2f /* Skip handling the SMC */
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1:
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mov r1, #0 /* cookie */
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bl handle_runtime_svc
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2:
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/* r0 points to smc context */
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/* Restore SCR from stack */
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pop {r1, r2}
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stcopr r1, SCR
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isb
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b sp_min_exit
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endfunc handle_smc
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/*
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* The Warm boot entrypoint for SP_MIN.
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*/
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func sp_min_warm_entrypoint
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/*
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* On the warm boot path, most of the EL3 initialisations performed by
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* 'el3_entrypoint_common' must be skipped:
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*
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* - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by
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* programming the reset address do we need to set the CPU endianness.
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* In other cases, we assume this has been taken care by the
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* entrypoint code.
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*
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* - No need to determine the type of boot, we know it is a warm boot.
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*
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* - Do not try to distinguish between primary and secondary CPUs, this
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* notion only exists for a cold boot.
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*
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* - No need to initialise the memory or the C runtime environment,
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* it has been done once and for all on the cold boot path.
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*/
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el3_entrypoint_common \
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_set_endian=PROGRAMMABLE_RESET_ADDRESS \
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_warm_boot_mailbox=0 \
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_secondary_cold_boot=0 \
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_init_memory=0 \
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_init_c_runtime=0 \
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_exception_vectors=sp_min_vector_table
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/* --------------------------------------------
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* Enable the MMU with the DCache disabled. It
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* is safe to use stacks allocated in normal
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* memory as a result. All memory accesses are
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* marked nGnRnE when the MMU is disabled. So
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* all the stack writes will make it to memory.
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* All memory accesses are marked Non-cacheable
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* when the MMU is enabled but D$ is disabled.
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* So used stack memory is guaranteed to be
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* visible immediately after the MMU is enabled
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* Enabling the DCache at the same time as the
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* MMU can lead to speculatively fetched and
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* possibly stale stack memory being read from
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* other caches. This can lead to coherency
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* issues.
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* --------------------------------------------
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*/
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mov r0, #DISABLE_DCACHE
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bl bl32_plat_enable_mmu
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bl sp_min_warm_boot
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/* Program the registers in cpu_context and exit monitor mode */
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mov r0, #NON_SECURE
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bl cm_get_context
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/* Restore the SCR */
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ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR]
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stcopr r2, SCR
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isb
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/* Restore the SCTLR */
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ldr r2, [r0, #CTX_REGS_OFFSET + CTX_NS_SCTLR]
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stcopr r2, SCTLR
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bl smc_get_next_ctx
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/* The other cpu_context registers have been copied to smc context */
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b sp_min_exit
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endfunc sp_min_warm_entrypoint
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/*
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* The function to restore the registers from SMC context and return
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* to the mode restored to SPSR.
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*
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* Arguments : r0 must point to the SMC context to restore from.
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*/
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func sp_min_exit
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smcc_restore_gp_mode_regs
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eret
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endfunc sp_min_exit
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